ISO7221CDR

Part: ISO722x Dual-Channel Digital Isolators from Texas Instruments

Type: Dual-Channel Digital Isolator

Key Specs:

• Signaling Rate: 1, 5, 25, and 150Mbps
• Channel-to-Channel Output Skew: 1ns Max
• Pulse-Width Distortion (PWD): 1ns Max
• Jitter Content: 1ns Typ at 150Mbps
• Transient Immunity: 50kV/μs Typical
• Supply Voltages: 2.8V (C-Grade), 3.3V, or 5V
• ESD Protection: 4kV
• Operating Range: -40°C to +125°C
• Galvanic Isolation: up to 4000Vpk
• Output Current: -15mA to 15mA

Features:

• Low Channel-to-Channel Output Skew
• Low Pulse-Width Distortion (PWD)
• Low Jitter Content
• High Electromagnetic Immunity
• Typical 28-Year Life at Rated Voltage
• Safety Related Certifications: DIN EN IEC 60747-17 (VDE 0884-17), UL 1577, IEC 61010-1, IEC 62368-1
• Failsafe circuit drives output to logic high if input unpowered or not actively driven
• Inputs are 5V tolerant when supplied from 2.8V or 3.3V supply
• Outputs are 4mA CMOS

Applications:

• Factory Automation
• Computer Peripheral Interface
• Servo Control Interface
• Data Acquisition

Package:

• ISO7220x: D (SOIC, 8): Body Size 4.90mm × 3.91mm, Package Size 4.9mm × 6mm
• ISO7221x: D (3010, 8): Body Size 4.90mm × 3.91mm, Package Size 4.911111 ^ 011111

• 1, 5, 25, and 150Mbps Signaling Rate Options
  • Low Channel-to-Channel Output Skew; 1ns Max
  • Low Pulse-Width Distortion (PWD); 1ns Max
  • Low Jitter Content; 1ns Typ at 150Mbps
• 50kV/μs Typical Transient Immunity
• Operates with 2.8V (C-Grade), 3.3V, or 5V Supplies
• 4kV ESD Protection
• High Electromagnetic Immunity
• -40°C to +125°C Operating Range
• Typical 28-Year Life at Rated Voltage (see Isolation Lifetime Projection)
• Safety Related Certifications
  • DIN EN IEC 60747-17 (VDE 0884-17) conformity per VDE
  • UL 1577 component recognition program
  • IEC 61010-1, IEC 62368-1 certifications

• Factory Automation
  • Modbus
  • Profibus™
  • DeviceNet^™ Data Buses
• Computer Peripheral Interface
• Servo Control Interface
• Data Acquisition

3 Description

The ISO7220x and ISO7221x family devices are dualchannel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220x and in opposite directions in the ISO7221x. These devices have a logic input and output buffer separated by TI's silicon-dioxide (SiO₂) isolation barrier, providing galvanic isolation of up to 4000V_PK per VDE. Used in conjunction with isolated power supplies, these devices block high voltage and isolate grounds, as well as prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, then differentiated by the isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to verify that the proper dc level of the

output. If this dc-refresh pulse is not received every 4μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.

The resulting time constant provide fast operation with signaling rates available from 0Mbps (DC) to 150Mbps (The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps). The A-option, B-option, and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS V_CC/2 input thresholds and do not have the input noise filter and the additional propagation delay.

The ISO7220x and ISO7221x family of devices require two supply voltages of 2.8V (C-Grade), 3.3V, 5V, or any combination. All inputs are 5V tolerant when supplied from a 2.8V or 3.3V supply and all outputs are 4mA CMOS.

The ISO7220x and ISO7221x family of devices are characterized for operation over the ambient temperature range of -40°C to +125°C.

Package Information

• For all available packages, see the orderable addendum at the end of the data sheet.
• The package size (length × width) is a nominal value and includes pins, where applicable.

V_CCI and GNDI are supply and ground connections respectively for the input channels.

V_CCO and GNDO are supply and ground connections respectively for the output channels.

Simplified Schematic

Figure 4-1. ISO7220x D Package 8-Pin SOIC Top View

Figure 4-2. ISO7221x D Package 8-Pin SOIC Top View

Table 4-1. Pin Functions

VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted.)

over operating free-air temperature range (unless otherwise noted)(1)

• (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
• (2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
• (3) Maximum voltage must not exceed 6 V.

⁽¹⁾ Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C.

⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Power Ratings

VCC1 = VCC2 = 5.5 V, T^J = 150C, CL = 15 pF, Input a 150 Mbps 50% duty cycle square wave

⁽²⁾ For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.

For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.

For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8 V.

⁽²⁾ Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.

5.6 Insulation Specifications

• (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
• (2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
• (3) Apparent charge is electrical discharge caused by a partial discharge (pd).
• (4) All pins on each side of the barrier tied together creating a two-terminal device

5.7 Safety-Related Certifications

5.8 Safety Limiting Values

Safety limiting⁽¹⁾ intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.