ISO1050

Part: ISO1050, Texas Instruments

Type: Isolated CAN Transceiver

Key Specs:

• Isolation: 5000 VRMS (ISO1050DW)
• Isolation: 2500 VRMS (ISO1050DUB)
• Loop delay: 150 ns (typical), 210 ns (maximum)
• Transient immunity: 50 kV/μs (typical)
• Bus-fault protection: –27 V to 40 V
• I/O voltage range: 3.3 V and 5 V
• Signaling rates: up to 1 Mbps
• Ambient temperature range: –55°C to 105°C

Features:

• Meets the requirements of ISO11898-2
• Fail-safe outputs
• Driver (TXD) dominant time-out function
• Safety-related certifications (VDE, UL, CSA, TUV, CQC approvals)
• Typical 25-year life at rated working voltage

Applications:

• Industrial automation, control, sensors, and drive systems
• Building and climate control (HVAC) automation
• Security systems
• Transportation
• Medical
• Telecom
• CAN bus standards such as CANopen, DeviceNet, NMEA2000, ARINC825, ISO11783, CAN Kingdom, CANaerospace

Package:

• SOP (8): dimensions not specified
• SOIC (16): dimensions not specified

• Meets the requirements of ISO11898-2
• 5000-VRMS isolation (ISO1050DW)
• 2500-VRMS isolation (ISO1050DUB)
• Fail-safe outputs
• Low loop delay: 150 ns (typical), 210 ns (maximum)
• 50-kV/μs typical transient immunity
• Bus-fault protection of –27 V to 40 V
• Driver (TXD) dominant time-out function
• I/O voltage range supports 3.3 V and 5 V microprocessors
• Safety-related certifications
  • VDE approval per DIN EN IEC 60747-17 (VDE 0884-17)
  • UL 1577 approved
  • CSA approved for IEC 61010-1, IEC 60601-1
  • TUV Reinforced Insulation Approval for EN/UL/CSA 62368-1 (ISO1050DW-Only)
  • CQC reinforced insulation per GB4943.1 (ISO1050DW-only)
  • Typical 25-year life at rated working voltage (see application report SLLA197 and Life Expectancy vs Working Voltage)

• Industrial automation, control, sensors, and drive systems
• Building and climate control (HVAC) automation
• Security systems
• Transportation
• Medical
• Telecom
• CAN bus standards such as CANopen, DeviceNet, NMEA2000, ARINC825, ISO11783, CAN Kingdom, CANaerospace

Figure 5-1. 16-Pin DW Package Top View

Table 5-1. Pin Functions

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Typical specifications are at V_CC1 = 3.3V , V_CC2 = 5V , Min/Max are over recommended operating conditions (unless otherwise noted)

Product Folder Links: ISO1050

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Typical specifications are at VCC1 = 3.3V, VCC2 = 5V, Min/Max are over recommended operating conditions (unless otherwise noted)

6.10 Switching Characteristics

Typical specifications are at V_CC1 = 3.3V, V_CC2 = 5V, Min/Max are over recommended operating conditions (unless otherwise noted)

6.11 Insulation Characteristics Curves

Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ISO1050

6.12 Typical Characteristics

7 Parameter Measurement Information

Figure 7-1. Driver Voltage, Current and Test Definitions

Figure 7-2. Bus Logic State Voltage Definitions

Figure 7-3. Driver V_OD With Common-Mode Loading Test Circuit

• A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, t_r ≤ 6 ns, t_f ≤ 6 ns, Z_O = 50 Ω.
• B. C_L includes instrumentation and fixture capacitance within ± 20% .

Figure 7-4. Driver Test Circuit and Voltage Waveforms

label{localization} {it Copyright @ 2023 Texas Instruments Incorporated} {it Product Folder Links: } textit{ISO1050}

Figure 7-5. Receiver Voltage and Current Definitions

• A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, t^r ≤ 6 ns, t^f ≤ 6 ns, ZO = 50 Ω.
• B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 7-6. Receiver Test Circuit and Voltage Waveforms

Table 7-1. Differential Input Voltage Threshold Test

The waveforms of the applied transients are in accordance with ISO 7637 part 1, test pulses 1, 2, 3a, and 3b.

Figure 7-7. Transient Overvoltage Test Circuit

Figure 7-8. Peak-to-Peak Output Voltage Test Circuit and Waveform

Figure 7-9. tLOOP Test Circuit and Voltage Waveforms

• A. The input pulse is supplied by a generator having the following characteristics: t^r ≤ 6 ns, t^f ≤ 6 ns, ZO = 50 Ω.
• B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 7-10. Dominant Time-out Test Circuit and Voltage Waveforms

Figure 7-11. Driver Short-Circuit Current Test Circuit and Waveforms

Figure 7-12. Fail-Safe Delay Time Test Circuit and Voltage Waveforms

Figure 7-13. Common-Mode Transient Immunity Test Circuit

Figure 7-14. Electromagnetic Emissions Measurement Setup

8 Detailed Description

8.1 Overview

The ISO1050 is a digitally isolated CAN transceiver with a typical transient immunity of 50 kV/μs. The device can operate from 3.3-V supply on side 1 and 5-V supply on side 2. This is of particular advantage for applications operating in harsh industrial environments because the 3.3 V on side 1 enables the connection to low-volt microcontrollers for power preservation, whereas the 5 V on side 2 maintains a high signal-to-noise ratio of the bus signals.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 CAN Bus States

The CAN bus has two states during operation: dominant and recessive. A dominant bus state, equivalent to logic low, is when the bus is driven differentially by a driver. A recessive bus state is when the bus is biased to a common mode of VCC / 2 through the high-resistance internal input resistors of the receiver, equivalent to a logic high. The host microprocessor of the CAN node will use the TXD pin to drive the bus and will receive data from the bus on the RXD pin. See Figure 8-1 and Figure 8-2.

Figure 8-1. Bus States (Physical Bit Representation)

Figure 8-2. Simplified Recessive Common Mode Bias and Receiver

8.3.2 Digital Inputs and Outputs

TXD (Input) and RXD (Output):

V_CC1 for the isolated digital input and output side of the device maybe supplied by a 3.3-V or 5-V supply and thus the digital inputs and outputs are 3.3-V and 5-V compatible.

Note

TXD is very weakly internally pulled up to V_CC1 . An external pullup resistor should be used to make sure that TXD is biased to recessive (high) level to avoid issues on the bus if the microprocessor doesn't control the pin and TXD floats. TXD pullup strength and CAN bit timing require special consideration when the device is used with an open-drain TXD output on the CAN controller of the microprocessor. An adequate external pullup resistor must be used to ensure that the TXD output of the microprocessor maintains adequate bit timing input to the input on the transceiver.

8.3.3 Protection Features

8.3.3.1 TXD Dominant Time-Out (DTO)

TXD DTO circuit prevents the local node from blocking network communication in the event of a hardware or software failure where TXD is held dominant longer than the time-out period t_TXDDTO . The TXD DTO circuit timer starts on a falling edge on TXD. The TXD DTO circuit disables the CAN bus driver if no rising edge is seen before the time-out period expires. This frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a recessive signal is seen on the TXD pin, thus clearing the TXD DTO condition. The receiver and RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD dominant time-out.

Note

The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_TXDDTO minimum, limits the minimum data rate. Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / t_TXDDTO .

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Figure 8-3. Example Timing Diagram for Devices With TXD DTO

8.3.3.2 Thermal Shutdown

If the junction temperature of the device exceeds the thermal shut down threshold the device turns off the CAN driver circuits thus blocking the TXD to bus transmission path. The shutdown condition is cleared when the junction temperature drops below the thermal shutdown temperature of the device. If the fault condition is still present, the temperature may rise again and the device would enter thermal shut down again. Prolonged operation with thermal shutdown conditions may affect device reliability.

Note

During thermal shutdown the CAN bus drivers turn off; thus no transmission is possible from TXD to the bus. The CAN bus pins are biased to recessive level during a thermal shutdown, and the receiver to RXD path remains operational.

8.3.3.3 Undervoltage Lockout and Fail-Safe

The supply pins have undervoltage detection that places the device in protected or fail-safe mode. This protects the bus during an undervoltage event on VCC1 or VCC2 supply pins. If the bus-side power supply VCC2 is lower than about 4 V, the power shutdown circuits in the ISO1050 will disable the transceiver to prevent false transmissions due to an unstable supply. If VCC1 is still active when this occurs, the receiver output (RXD) will go to a fail-safe HIGH (recessive) value in about 6 microseconds.

Table 8-1. Undervoltage Lockout and Fail-Safe

Note

After an undervoltage condition is cleared and the supplies have returned to valid levels, the device typically resumes normal operation in 300 μs

8.3.3.4 Floating Pins

Pullups and pulldowns should be used on critical pins to place the device into known states if the pins float. The TXD pin should be pulled up through a resistor to VCC1 to force a recessive input level if the microprocessor output to the pin floats.

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8.3.3.5 CAN Bus Short-Circuit Current Limiting

The device has several protection features that limit the short-circuit current when a CAN bus line is shorted. These include driver current limiting (dominant and recessive). The device has TXD dominant state time out to prevent permanent higher short-circuit current of the dominant state during a system fault. During CAN communication the bus switches between dominant and recessive states with the data and control fields bits, thus the short-circuit current may be viewed either as the instantaneous current during each bus state, or as a DC average current. For system current (power supply) and power considerations in the termination resistors and common-mode choke ratings, use the average short-circuit current. Determine the ratio of dominant and recessive bits by the data in the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at certain times:

• Control fields with set bits
• Bit-stuffing
• Interframe space
• TXD dominant time-out (fault case limiting)

These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage of dominant bits.

Note

The short-circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short-circuit currents. The average short-circuit current may be calculated with the following formula:

IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC]

Where

• IOS(AVG) is the average short-circuit current.
• %Transmit is the percentage the node is transmitting CAN messages.
• %Receive is the percentage the node is receiving CAN messages.
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages.
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages.
• IOS(SS)_REC is the recessive steady state short-circuit current.
• IOS(SS)_DOM is the dominant steady state short-circuit current.

Note

Consider the short-circuit current and possible fault cases of the network when sizing the power ratings of the termination resistance and other network components.

8.4 Device Functional Modes

Table 8-2. Driver Function Table

Product Folder Links: ISO1050

(1) H = high level, L = low level, ? = indeterminate.

Table 8-4. Function Table

Figure 8-4. Equivalent I/O Schematics

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

ISO1050 can be used with other components from TI such as a microcontroller, a transformer driver, and a linear voltage regulator to form a fully isolated CAN interface.

9.2 Typical Application

Figure 9-1. Application Circuit

9.2.1 Design Requirements

Unlike optocoupler-based solution, which needs several external components to improve performance, provide bias, or limit current, ISO1050 only needs two external bypass capacitors to operate.

9.2.2 Detailed Design Procedure

9.2.2.1 Bus Loading, Length and Number of Nodes

The ISO11898 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high number of nodes requires a transceiver with high input impedance such as the ISO1050.

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Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO11898 standard. They have made system level trade offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these specifications are ARINC825, CANopen, CAN Kingdom, DeviceNet and NMEA200.

A CAN network design is a series of tradeoffs, but these devices operate over wide –12-V to 12-V commonmode range. In ISO11898-2 the driver differential output is specified with a 60-Ω load (the two 120-Ω termination resistors in parallel) and the differential output must be greater than 1.5 V. The ISO1050 is specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential output of 1.4 V with a 45-Ω load. The differential input resistance of the ISO1050 is a minimum of 30 kΩ. If 167 ISO1050 transceivers are in parallel on a bus, this is equivalent to a 180-Ω differential load. That transceiver load of 180 Ω in parallel with the 60 Ω gives a total 45 Ω. Therefore, the ISO1050 theoretically supports over 167 transceivers on a single bus segment with margin to the 1.2-V minimum differential input at each node. However for CAN network design margin must be given for signal loss across the system and cabling, parasitic loadings, network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much lower. Bus length may also be extended beyond the original ISO11898 standard of 40 m by careful system design and data rate tradeoffs. For example, CAN open network design guidelines allow the network to be up to 1km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

This flexibility in CAN network design is one of the key strengths of the various extensions and additional standards that have been built on the original ISO11898 CAN standard. In using this flexibility comes the responsibility of good network design.

9.2.2.2 CAN Termination

The ISO11898 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded) with 120-Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination may be in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that it is not removed from the bus.

Figure 9-2. Typical CAN Bus

Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used. (See Figure 9-3). Split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.

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Figure 9-3. CAN Bus Termination Concepts

9.2.3 Application Curve

Figure 9-4. Life Expectancy vs Working Voltage (ISO1050DUB)

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Product Folder Links: ISO1050

10 Power Supply Recommendations

10.1 General Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side using Texas Instruments' SN6505 and SN6501 based power supply solution. For such applications, detailed power supply design and transformer selection recommendations are available in SN6505 and SN6501 data sheets (SLLSEP9, SLLSEA0).

10.2 Power Supply Discharging

To ensure normal re-initialization time after a power down, the power supply for the ISO1050 needs to discharge below 0.3 V, and as closely to 0 V as possible, to ensure that a communication delay does not occur. Figure 10-1 illustrates various scenarios of power-supply ramp-down and its effect on the communication delay.

Figure 10-1. Power Supply Ramp-Down and Communication Delay Behavior

The brownout window, 0.3 V to 1.3 V (typical), represents the range of voltage in which a longer than normal reinitialization time may occur if VCC2 powers up from this voltage. The ISO1042, an upgraded device with higher isolation rating, CAN FD speeds of 5 Mbps, higher bus fault-protection voltage, stronger EMC performance, and smaller package options does not exhibit this behavior. For all new isolated CAN designs, it is recommended to use the ISO1042. If the ISO1050 must be used, ensure that VCC2 discharges to 0 V so that a longer than normal re-initialization time does not exist. If the power supplies cannot be configured in such a way that VCC2 discharge below 0.3 V on their own, implement a bleed resistor between VCC2 and GND2. The bleed resistor value should be selected such that it ensures VCC2 goes below the brownout window fast enough for any power interruption or power down sequence the system may permit. The lower the resistance, the faster VCC2 will discharge to 0V with the tradeoff of consuming power. For many systems, a bleed resistor value of 2 KΩ is sufficient.

11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 11-1). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and lowfrequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in² .
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.

11.1.1 PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and its self-extinguishing flammability-characteristics.

11.2 Layout Example

Figure 11-1. Recommended Layer Stack

Product Folder Links: ISO1050

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

• Texas Instruments, *High-Voltage Lifetime of the ISO72x Family of Digital Isolators*application report
• Texas Instruments, SN6505x Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet
• Texas Isntruments, Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, Digital Isolator Design Guide application report
• Texas Instruments, Isolation Glossary application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Over operating free-air temperature range (unless otherwise noted)(1) (2)

• (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
• (2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
• (3) Maximum voltage must not exceed 6 V

Product Folder Links: ISO1050

6.5 Power Ratings

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6.6 Insulation Specifications

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⁽²⁾ ISO1044 is suitable for basic electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

⁽³⁾ Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

⁽⁴⁾ Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications