IS31FL3731

Part 1: Markdown Summary

Part: IS31FL3731 from Integrated Silicon Solution, Inc.

Type: Audio Modulated Matrix LED Driver

Key Specs:

• Supply voltage range: 2.7V to 5.5V
• Number of LEDs: 144 single LEDs
• I2C-compatible interface speed: 400kHz
• Individual LED dimming: 8-bit (256 steps)
• Operating temperature range: -40°C to +85°C
• Average current of each LED: 3.2mA (when REXT = 20kΩ)

Features:

• Supply voltage range: 2.7V to 5.5V
• 400kHz I2C-compatible interface
• 144 LEDs in dot matrix
• Individual blink control
• 8 frames memory for animations
• Picture mode and animation mode
• Auto intensity breathing during the switching of different frames
• LED frames displayed can be modulated with audio signal intensity
• LED light intensity can be modulated with audio signal intensity
• QFN-28 (4mm × 4mm) and SSOP-28 package

Applications:

• Mobile phones and other hand-held devices for LED display
• LED in home appliances

Package:

• QFN-28: 4mm × 4mm
• SSOP-28: dimensions not specified

• Supply voltage range: 2.7V to 5.5V
• 400kHz I2C-compatible interface
• 144 LEDs in dot matrix
• Individual blink control
• 8 frames memory for animations
• Picture mode and animation mode
• Auto intensity breathing during the switching of different frames
• LED frames displayed can be modulated with audio signal intensity
• LED light intensity can be modulated with audio signal intensity
• QFN-28 (4mm × 4mm) and SSOP-28 package

APPLICATIONS

• Mobile phones and other hand-held devices for LED display
• LED in home appliances

Figure 1 Typical Application Circuit

Note 1: The IC should be placed far away from the mobile antenna in order to prevent the EMI.

Note 2: The average current of each LED is 3.2mA when REXT = 20kΩ. The LED current can be modulated by the REXT. Please refer to the detail information in Page 18.

TYPICAL APPLICATION CIRCUIT

• Mobile phones and other hand-held devices for LED display
• LED in home appliances

• QFN-28
• SSOP-28

Symbol	Parameter	Conditions	Min.	Typ.	Max.	Unit
VCC	Supply voltage		2.7		5.5	V
ICC	Quiescent power supply current	VIN = 0V, without audio input, all LEDs off		2.17		mA
ISD Shutdown current		VSDB = 0V VSDB = VCC, software shutdown		0.5 230	5	μA
IOUT	Output current of C1~C9	Matrix display mode without audio modulation		34 (Note 1)		mA
	Current sink headroom voltage C1~C9	Isink = 270mA (Note 2)		400		mV
VHR	Current source headroom voltage C1~C9	Isource = 34mA		400
tSCAN	Period of scanning (Figure 2)			106		μs
tSCANOL	Non-overlap blanking time during scan (Figure 2)			15		μs
ILED	Average current of each LED	REXT = 20kΩ, PWM in 255 step (Note 3)		3.2		mA
Logic Electrical Characteristics (SDA, SCL, AD)
VIL	Logic "0" input voltage	VCC = 2.7V			0.4	V
VIH	Logic "1" input voltage	VCC = 5.5V	1.4			V
IIL	Logic "0" input current	VINPUT = 0V		5 (Note 4)		nA
IIH	Logic "1" input current	VINPUT = VCC		5 (Note 4)		nA

DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 4)

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
fSCL	Serial-Clock frequency				400	kHz
tBUF	Bus free time between a STOP and a START condition		1.3			μs
tHD, STA	Hold time (repeated) START condition		0.6			μs
tSU, STA	Repeated START condition setup time		0.6			μs
tSU, STO	STOP condition setup time		0.6			μs
tHD, DAT	Data hold time				0.9	μs
tSU, DAT	Data setup time		100			ns
tLOW	SCL clock low period		1.3			μs
tHIGH	SCL clock high period		0.7			μs
tR	Rise time of both SDA and SCL signals, receiving	(Note 5)		20+0.1Cb	300	ns
tF	Fall time of both SDA and SCL signals, receiving	(Note 5)		20+0.1Cb	300	ns

Note 1: The average current of each LED is IOUT/10.5.

Note 2: All LEDs are on.

Note 3: ILED = 64.7/REXT, REXT = 20kΩ is recommended. The recommended minimum value of REXT is 18kΩ, or it may cause a large current. Note 4: Guaranteed by design.

Note 5: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC.

Figure 2 Scanning timing

DETAILED DESCRIPTION

I2C INTERFACE

The IS31FL3731 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires: SCL and SDA. The IS31FL3731 has a 7-bit slave address (A7:A1), followed by the R/W bit, A0. Set A0 to "0" for a write command and set A0 to "1" for a read command. The value of bits A1 and A2 are decided by the connection of the AD pin.

The complete slave address is:

Table 1 Slave Address (Write only):

Bit	A7:A3	A2:A1	A0
Value	11101	AD	0/1

AD connected to GND, AD=00;

AD connected to VCC, AD=11; AD connected to SCL, AD=01; AD connected to SDA, AD=10;

The SCL line is uni-directional. The SDA line is bidirectional (open-collector) with a pull-up resistor (typically 4.7kΩ). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the microcontroller and the slave is the IS31FL3731.

The timing diagram for the I2C is shown in Figure 3. The SDA is latched in on the stable high level of the SCL. When there is no interface activity, the SDA line should be held high.

The "START" signal is generated by lowering the SDA signal while the SCL signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own chip address.

The 8-bit chip address is sent next, most significant bit first. Each address bit must be stable while the SCL level is high.

After the last bit of the chip address is sent, the master checks for the IS31FL3731's acknowledge. The master releases the SDA line high (through a pull-up resistor). Then the master sends an SCL pulse. If the IS31FL3731 has received the address correctly, then it holds the SDA line low during the SCL pulse. If the SDA line is not low, then the master should send a "STOP" signal (discussed later) and abort the transfer.

Following acknowledge of IS31FL3731, the register address byte is sent, most significant bit first. IS31FL3731 must generate another acknowledge indicating that the register address has been received.

Then 8-bit of data byte are sent next, most significant bit first. Each data bit should be valid while the SCL level is stable high. After the data byte is sent, the IS31FL3731 must generate another acknowledge to indicate that the data was received.

The "STOP" signal ends the transfer. To signal "STOP", the SDA signal goes high while the SCL signal is high.

ADDRESS AUTO INCREMENT

To write multiple bytes of data into IS31FL3731, load the address of the data register that the first data byte is intended for. During the IS31FL3731 acknowledge of receiving the data byte, the internal address pointer will increment by one. The next data byte sent to IS31FL3731 will be placed in the new address, and so on. The auto increment of the address will continue as long as data continues to be written to IS31FL3731 (Figure 6).

READING PORT REGISTERS

All of registers in IS31FL3731 can be read. But Frame Registers can only be read in software shutdown mode as SDB pin is high. The Function Register can be read in software shutdown mode or operating mode.

To read the device data, the bus master must first

send the IS31FL3731 address with the R/W____ bit set to "0", followed by the Command Register address, FDh, then send command data which determines which response register is accessed. After a restart, the bus master must send the IS31FL3731 address with the

R/W____ bit set to "0" again, followed by the register address which determines which register is accessed. Then restart I2C, the bus master should send the

IS31FL3731 address with the R/W____ bit set to "1". Data from the register defined by the command byte is then sent from the IS31FL3731 to the master (Figure 7).

Figure 4 Bit transfer

Figure 6 Writing to IS31FL3731(Automatic address increment)

Figure 7 Reading from IS31FL3731

REGISTER DEFINITION Table 2 FDh Command Register

Data	Function	Data	Function
0000 0000	Point to Page One(Frame 1 Register is available)	0000 0001	Point to Page Two(Frame 2 Register is available)
0000 0010	Point to Page Three(Frame 3 Register is available)	0000 0011	Point to Page Four(Frame 4 Register is available)
0000 0100	Point to Page Five(Frame 5 Register is available)	0000 0101	Point to Page Six(Frame 6 Register is available)
0000 0110	Point to Page Seven(Frame 7 Register is available)	0000 0111	Point to Page Eight(Frame 8 Register is available)
0000 1011	Point to Page Nine(Function Register is available)	Others	Reserved

Note: The Command Register should be configured first after writing in the slave address to choose the available register (Frame Registers and Function Registers). Then write data in the choosing register.

For example, when write "0000 0011" in the Command Register (FDh), the data which writing after will be stored in the Frame 4 Register. Write new data can configure other registers.

Table 3 Response Register Function (The address of each Page is starting from 00h. Frame Registers have the same format.)

Address	Name	Function	R/W	Default
	Frame Register (Page One to Page Eight) (Note 6)
00h ~ 11h	LED Control Register	Store on or off state for each LED	R/W
12h ~ 23h	Blink Control Register	Control the blink function for each LED	R/W	xxxx xxxx
24h ~ B3h	PWM Register	144 LEDs PWM duty cycle data register	R/W
	Function Register (Page Nine
Note 6: The data of Frame Registers is not assured when power on. Please initialize the Frame Registers first to ensure operate normally. Note 7: The 04h register has no function although it can be written. It also can be read but the data is not assured.

Supply voltage, VCC	-0.3V ~ +5.5V
Voltage at any input pin	-0.3V ~ VCC+0.3V
Maximum junction temperature, TJMAX	150°C
Storage temperature range, TSTG	-65°C ~ +150°C
Operating temperature range, TA	-40°C ~ +85°C

Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.