ENC424J600T

Part: ENC424J600/ENC624J600 (ENC424J600-I/PT) — Microchip Technology

Type: Stand-Alone 10/100 Ethernet Controller (integrated MAC and PHY) with SPI or Parallel Interface

Description: IEEE 802.3-compliant 10/100Base-T Ethernet controller with integrated MAC and PHY, 24-Kbyte packet buffer SRAM, hardware security engines, and a 14 Mbit/s SPI or parallel host interface, operating from 3.0–3.6 V.

Operating Conditions:

• Supply voltage: 3.0–3.6 V
• Operating temperature: -40 to +85 °C (industrial)
• Clock: 25 MHz
• Digital inputs are 5 V tolerant

Absolute Maximum Ratings:

• Voltage on VDD, VDDOSC, VDDPLL, VDDRX and VDDTX with respect to VSS: -0.3 to 4.0 V
• Voltage on any digital pin with respect to VSS: -0.3 to 6.0 V
• Current into all VDD pins: 300 mA
• Current out of all VSS pins: 420 mA
• Current sourced or sunk by any digital output pin: 25 mA
• Storage temperature: -65 to +150 °C
• Ambient temperature under bias: -40 to +85 °C
• ESD protection on all pins: 2 kV

Key Specs:

• Supply voltage range: 3.0–3.6 V
• Ethernet speed: 10/100 Mbps, half and full duplex, with auto-negotiation
• SPI interface: up to 14 Mbit/s
• Parallel interface: up to 160 Mbit/s (demultiplexed 16-bit, 64-pin device)
• Packet buffer: 24 Kbyte SRAM (12K x 16)
• Clock output: programmable 50 kHz to 33.3 MHz
• Security engines: modular exponentiation up to 1024-bit, AES 128/192/256-bit, MD5, SHA-1
• Internal interrupt sources: 11, mappable to a single external interrupt

Features:

• Integrated MAC and 10/100Base-T PHY with automatic polarity detection and correction
• Hardware security acceleration engines (RSA, Diffie-Hellman, AES, MD5, SHA-1)
• Pause control frames with automatic transmit and receive flow control
• Programmable receive filters including Magic Packet, unicast, multicast, broadcast, pattern match and hash match
• Internal DMA and hardware IP checksum calculation
• Factory-preprogrammed unique MAC address
• Energy Detect Power-Down mode and internal loopback mode
• Two LED indicator outputs
• ENC424J600 (44-pin): SPI and 8-bit multiplexed parallel interface
• ENC624J600 (64-pin): additionally 16-bit multiplexed and 8/16-bit demultiplexed parallel interface

Applications:

• Ethernet network interface for any microcontroller with an SPI or parallel port
• Embedded systems requiring SSL/TLS cryptographic acceleration

Package:

• 44-pin TQFP (ENC424J600)
• 44-pin QFN (ENC424J600)
• 64-pin TQFP (ENC624J600)

Due to the high bandwidth and long cable length requirements, Ethernet applications can utilize a significant amount of power. ENC424J600/624J600 devices include power-down and PHY power management features to assist low-power applications. While features cannot completely mitigate power requirements, they can help reduce power consumption when the Ethernet interface is not needed.

TABLE 17-1: THERMAL OPERATING CONDITIONS

TABLE 17-2: THERMAL PACKAGING CHARACTERISTICS

TABLE 17-3: DC CHARACTERISTICS: ENC424J600/624J600 (INDUSTRIAL)

• 2: Cryptographic engine module disabled (EIR<15> = 0 ), auto-negotiation disabled (PHCON1<12> = 0 ) and Ethernet disabled (ECON2<15> = 0 ).
• 3: Measured across 100 Ω termination on cable side of transformer.

Note 1: VCAP is not designed to supply an external load. No external voltage should be applied to this pin.

† Notice: Stresses above those listed under 'Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.