Part: EFR32MG24B210F1536IM48-B — Silicon Labs

Type: Wireless SoC

Description: 32-bit ARM Cortex-M33 core with 78 MHz maximum operating frequency, up to 1536 kB Flash and 256 kB RAM, high performance 2.4 GHz radio with up to +19.5 dBm output power, and Secure Vault™.

Operating Conditions:

• Supply voltage: 1.71–3.8 V
• Operating temperature: -40 to +125 °C
• Max HCLK and SYSCLK frequency: 78 MHz (VSCALE2, MODE = WS1)

Absolute Maximum Ratings:

• Max supply voltage: 3.8 V
• Max continuous current: 200 mA (Total current into VDD power lines, Source)
• Max junction temperature: +125 °C

Key Specs:

• CPU: ARM Cortex-M33
• Max CPU frequency: 78 MHz
• Flash memory: Up to 1536 kB
• RAM data memory: Up to 256 kB
• 2.4 GHz RX current: 4.4 mA (1 Mbps GFSK)
• 2.4 GHz TX current: 5 mA (@ 0 dBm output power)
• DeepSleep current: 1.3 μA (16 kB RAM retention and RTC running from LFRCO)
• RF sensitivity: -105.4 dBm (@ 250 kbps O-QPSK DSSS)
• TX power: Up to 19.5 dBm
• ADC resolution/speed: 12-bit @ 1 Msps or 16-bit @ 76.9 ksps

Features:

• High Performance 32-bit 78 MHz ARM Cortex-M33 with DSP instruction and floating-point unit
• 2.4 GHz radio operation
• Matrix Vector Processor for AI/ML acceleration
• Energy efficient design with low active and sleep currents
• Secure Vault™ with hardware cryptographic acceleration, True Random Number Generator (TRNG), ARM® TrustZone®, Secure Boot (Root of Trust Secure Loader), Secure Debug Unlock, DPA Countermeasures, Secure Key Management with PUF, Anti-Tamper, Secure Attestation
• Wide selection of MCU peripherals including Analog to Digital Converter (IADC), Analog Comparator (ACMP), Digital to Analog Converter (VDAC), General Purpose I/O pins, DMA Controller (LDMA), Peripheral Reflex System (PRS), Timers, Real Time Counters, Low Energy Timer, Pulse Counter, Watchdog Timer, Universal Synchronous/Asynchronous Receiver/Transmitter (USART), Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART), I2C interface, Low-Frequency RC Oscillator, Keypad scanner, Die temperature sensor
• Protocol support for Matter, OpenThread, Zigbee, Bluetooth Low Energy (BLE 5.3), Bluetooth Mesh, Proprietary 2.4 GHz, Multiprotocol, Direction finding using Angle-of-Arrival (AoA) and Angle-of-Departure (AoD)

Applications:

• Smart Home - Gateways and hubs, sensors, switches, door locks, smart plugs
• Lighting - LED bulbs, luminaires
• Building Automation - Gateways, sensors, switches, location services
• AI/ML - Predictive maintenance, glass break detection, wake-word detection

Package:

• QFN40 5 mm × 5 mm × 0.85 mm
• QFN48 6 mm × 6 mm × 0.85 mm

• 32-bit ARM® Cortex®-M33 core with 78 MHz maximum operating frequency
• Up to 1536 kB of flash and 256 kB of RAM
• High performance radio with up to +19.5 dBm output power
• Energy efficient design with low active and sleep currents
• Secure Vault™
• AI/ML Hardware Accelerator

• Smart Home - Gateways and hubs, sensors, switches, door locks, smart plugs
• Lighting - LED bulbs, luminaires
• Building Automation - Gateways, sensors, switches, location services
• AI/ML - Predictive maintenance, glass break detection, wake-word detection

EFR32MG24B210F1536IM48-B — QFN48 Pinout

Pin	Name	Type	Description
1	PC01	I/O	GPIO Port C, Pin 1 / DISP_SI
2	PC02	I/O	GPIO Port C, Pin 2 / DISP_SCLK
3	PC03	I/O	GPIO Port C, Pin 3 / DISP_SCLK
4	PD00	I/O	GPIO Port D, Pin 0 / PTI_DATA
5	PD01	I/O	GPIO Port D, Pin 1 / PTI_SYNC
6	PD02	I/O	GPIO Port D, Pin 2 / JOYSTICK*
7	PD03	I/O	GPIO Port D, Pin 3 / DBG_TDI / TRACECLK
8	PD04	I/O	GPIO Port D, Pin 4 / DBG_TDO_SWO / TRACED0
9	PD05	I/O	GPIO Port D, Pin 5 / PTI_SYNC
10	PD06	I/O	GPIO Port D, Pin 6 / TRACED1
11	PA00	I/O	GPIO Port A, Pin 0 / VCOM_RTS
12	PA01	I/O	GPIO Port A, Pin 1 / DBG_TCK_SWCLK
13	PA02	I/O	GPIO Port A, Pin 2 / DBG_TDI / TRACECLK
14	PA03	I/O	GPIO Port A, Pin 3 / DBG_TMS_SWDIO / TRACED0
15	PA04	I/O	GPIO Port A, Pin 4 / DBG_RESET / RESETn
16	PA05	I/O	GPIO Port A, Pin 5 / TRACED1
17	PA06	I/O	GPIO Port A, Pin 6 / TRACED3
18	PA07	I/O	GPIO Port A, Pin 7 / TRACED3
19	PB00	I/O	GPIO Port B, Pin 0 / VCOM_ENABLE
20	PB01	I/O	GPIO Port B, Pin 1 / UIF_BUTTON0
21	PB02	I/O	GPIO Port B, Pin 2 / UIF_LED0
22	PB03	I/O	GPIO Port B, Pin 3 / UIF_BUTTON1
23	PB04	I/O	GPIO Port B, Pin 4 / UIF_LED1
24	PB05	I/O	GPIO Port B, Pin 5 / VCOM_CTS
25	GND	P	Ground
26	VMCU_IN	P	MCU Supply Voltage Input (3.3V)
27	NC	—	No Connect
28	NC	—	No Connect
29	PC09	I/O	GPIO Port C, Pin 9 / DISP_ENABLE
30	PC08	I/O	GPIO Port C, Pin 8 / DISP_SCS
31	PC06	I/O	GPIO Port C, Pin 6 / DISP_EXTCOMIN
32	PC04	I/O	GPIO Port C, Pin 4 / VRF_IN
33	GND	P	Ground
34	VRF_IN	P	RF Supply Voltage Input
35	NC	—	No Connect
36	NC	—	No Connect
37	NC	—	No Connect
38	P36	I/O	GPIO Port P, Pin 36 / NC
39	P38	I/O	GPIO Port P, Pin 38 / TIC
40	P40	I/O	GPIO Port P, Pin 40 / P40
41	P41	I/O	GPIO Port P, Pin 41 / PA04 / DBG_TDI / TRACECLK
42	P43	I/O	GPIO Port P, Pin 43 / PA05 / TRACED1
43	P45	I/O	GPIO Port P, Pin 45 / PA07 / TRACED3
44	F1	I/O	GPIO Port F, Pin 1 / PA01 / DBG_TCK_SWCLK
45	F3	I/O	GPIO Port F, Pin 3 / PB00 / VCOM_ENABLE
46	F7	I/O	GPIO Port F, Pin 7 / PA09 / VCOM_RX
47	F9	I/O	GPIO Port F, Pin 9 / PA00 / VCOM_RTS
48	F11	I/O	GPIO Port F, Pin 11 / PB04 / UIF_LED1

Notes

• Package: QFN48 (7×7 mm)
• Pin numbering: Derived from the connector pin mapping diagram (P200 Upper Row and P201 Lower Row) showing the EFR32MG24B210F1536IM48 GPIO assignments to the BRD4186C Radio Board connectors.
• Mutually exclusive connections: PD02 and P06 are mutually exclusive (default: PD02). See diagram note: "*Mutually exclusive connections. Default: PD02 to P6."
• NC pins: Pins 27, 28, 35, 36, 37 are marked as No Connect in the source material.
• Power pins: VMCU_IN (Pin 26) supplies 3.3V to the MCU; VRF_IN (Pin 34) supplies RF section voltage.
• GND pins: Pins 25 and 33 are ground connections.

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T A =25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Due to on-chip circuitry (e.g., diodes), some EFR32MG24 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFR32MG24 supply pins are defined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD
• In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)
• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered with power applied to these supplies.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter	Symbol	Test Condition	Min	Typ	Max	Unit
Storage temperature range	T STG		-50	-	+150	°C
Voltage on any supply pin 1	V DDMAX		-0.3	-	3.8	V
Junction temperature	T JMAX	-I grade	-	-	+125	°C
Voltage ramp rate on any supply pin	V DDRAMPMAX		-	-	1.0	V / μs
Voltage on HFXO pins	V HFXOPIN		-0.3	-	1.2	V
DC voltage on any GPIO pin	V DIGPIN		-0.3	-	V IOVDD + 0.3	V
DC voltage on RESETn pin 2	V RESETn		-0.3	-	3.8	V
DC voltage on RF pin RF2G4_IO	V MAX2G4		-0.3	-	1.2	V
Total current into VDD power lines	I VDDMAX	Source	-	-	200	mA
Total current into VSS ground lines	I VSSMAX	Sink	-	-	200	mA
Current per I/O pin	I IOMAX	Sink	-	-	50	mA
Current per I/O pin		Source	-	-	50	mA
Current for all I/O pins	I IOALLMAX	Sink	-	-	200	mA
Current for all I/O pins		Source	-	-	200	mA

1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifications for more details.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD.

Table 4.4. Thermal Characteristics

Package	Board	Parameter	Symbol	Test Condition	Value	Unit
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Ambient	Θ JA	Still Air	29.2	°C/W
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Θ JB		15.2	°C/W
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Top Center	Ѱ JT		0.3	°C/W
40QFN (5x5mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Ѱ JB		11.2	°C/W
40QFN (5x5mm)	No Board	Thermal Resistance, Junction to Case	Θ JC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	24.6	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Ambient	Θ JA	Still Air	27.7	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Θ JB		14.6	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Top Center	Ѱ JT		0.69	°C/W
48QFN (6x6mm)	JEDEC - High Thermal Cond. (2s2p) 1	Thermal Resistance, Junction to Board	Ѱ JB		11.85	°C/W
48QFN (6x6mm)	No Board	Thermal Resistance, Junction to Case	Θ JC	Temperature controlled heat sink on top of package, all other sides of package insulated to prevent heat flow.	23	°C/W

1. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 9 Via to top internal plane of PCB.

Figure 7.1. QFN40 Package Drawing

Table 7.1. QFN40 Package Dimensions

Dimension	Min	Typ	Max
A	0.80	0.85	0.90
A1	0.00	0.02	0.05
A3	0.20 REF	0.20 REF	0.20 REF
b	0.15	0.20	0.25
D	4.90	5.00	5.10
E	4.90	5.00	5.10
D2	3.55	3.70	3.85
E2	3.55	3.70	3.85
e	0.40 BSC	0.40 BSC	0.40 BSC
L	0.30	0.40	0.50
K	0.20	-	-
R	0.075	-	-
aaa	0.10	0.10	0.10
bbb	0.07	0.07	0.07
ccc	0.10	0.10	0.10
ddd	0.05	0.05	0.05
eee	0.08	0.08	0.08
fff	0.10	0.10	0.10

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

5. Package external pad (epad) may have pin one chamfer.

MPN	Package	Temperature Range	Packing
EFR32MG24B210F1536IM48	M48	Industrial	N/A