EFR32MG24B210F1536IM48-B

Part: EFR32MG24B210F1536IM48-B — Silicon Labs

Type: Wireless SoC

Description: 32-bit ARM Cortex-M33 core with 78 MHz maximum operating frequency, up to 1536 kB Flash and 256 kB RAM, high performance 2.4 GHz radio with up to +19.5 dBm output power, and Secure Vault™.

Operating Conditions:

• Supply voltage: 1.71–3.8 V
• Operating temperature: -40 to +125 °C
• Max HCLK and SYSCLK frequency: 78 MHz (VSCALE2, MODE = WS1)

Absolute Maximum Ratings:

• Max supply voltage: 3.8 V
• Max continuous current: 200 mA (Total current into VDD power lines, Source)
• Max junction temperature: +125 °C

Key Specs:

• CPU: ARM Cortex-M33
• Max CPU frequency: 78 MHz
• Flash memory: Up to 1536 kB
• RAM data memory: Up to 256 kB
• 2.4 GHz RX current: 4.4 mA (1 Mbps GFSK)
• 2.4 GHz TX current: 5 mA (@ 0 dBm output power)
• DeepSleep current: 1.3 μA (16 kB RAM retention and RTC running from LFRCO)
• RF sensitivity: -105.4 dBm (@ 250 kbps O-QPSK DSSS)
• TX power: Up to 19.5 dBm
• ADC resolution/speed: 12-bit @ 1 Msps or 16-bit @ 76.9 ksps

Features:

• High Performance 32-bit 78 MHz ARM Cortex-M33 with DSP instruction and floating-point unit
• 2.4 GHz radio operation
• Matrix Vector Processor for AI/ML acceleration
• Energy efficient design with low active and sleep currents
• Secure Vault™ with hardware cryptographic acceleration, True Random Number Generator (TRNG), ARM® TrustZone®, Secure Boot (Root of Trust Secure Loader), Secure Debug Unlock, DPA Countermeasures, Secure Key Management with PUF, Anti-Tamper, Secure Attestation
• Wide selection of MCU peripherals including Analog to Digital Converter (IADC), Analog Comparator (ACMP), Digital to Analog Converter (VDAC), General Purpose I/O pins, DMA Controller (LDMA), Peripheral Reflex System (PRS), Timers, Real Time Counters, Low Energy Timer, Pulse Counter, Watchdog Timer, Universal Synchronous/Asynchronous Receiver/Transmitter (USART), Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART), I2C interface, Low-Frequency RC Oscillator, Keypad scanner, Die temperature sensor
• Protocol support for Matter, OpenThread, Zigbee, Bluetooth Low Energy (BLE 5.3), Bluetooth Mesh, Proprietary 2.4 GHz, Multiprotocol, Direction finding using Angle-of-Arrival (AoA) and Angle-of-Departure (AoD)

Applications:

• Smart Home - Gateways and hubs, sensors, switches, door locks, smart plugs
• Lighting - LED bulbs, luminaires
• Building Automation - Gateways, sensors, switches, location services
• AI/ML - Predictive maintenance, glass break detection, wake-word detection

Package:

• QFN40 5 mm × 5 mm × 0.85 mm
• QFN48 6 mm × 6 mm × 0.85 mm

• 32-bit ARM® Cortex®-M33 core with 78 MHz maximum operating frequency
• Up to 1536 kB of flash and 256 kB of RAM
• High performance radio with up to +19.5 dBm output power
• Energy efficient design with low active and sleep currents
• Secure Vault™
• AI/ML Hardware Accelerator

• Smart Home - Gateways and hubs, sensors, switches, door locks, smart plugs
• Lighting - LED bulbs, luminaires
• Building Automation - Gateways, sensors, switches, location services
• AI/ML - Predictive maintenance, glass break detection, wake-word detection

EFR32MG24B210F1536IM48-B — 48-VFQFN Pinout

Notes

• Exposed Pad (Pin 0): The package includes an exposed pad (VSS) at the center bottom of the die; this is not numbered in the standard pin count.
• Standard Device Variant: This pinout is for the Standard Device variant (Table 6.1), which includes PA08 and PA09 as GPIO pins and VREFP/VREFN as dedicated ADC reference inputs.
• ADC Variant Alternative: An ADC Device variant (Table 6.2) exists with different pin assignments at positions 18–27 (includes AIN0–AIN3 dedicated ADC inputs); confirm your specific variant matches the Standard Device configuration shown here.
• Crystal Pins: HFXTAL_I (pin 11) and HFXTAL_O (pin 12) require external high-frequency crystal oscillator.
• Power Supply Decoupling: External decoupling capacitor required at DECOUPLE pin (36).

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T A =25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Due to on-chip circuitry (e.g., diodes), some EFR32MG24 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFR32MG24 supply pins are defined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD
• In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)
• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered with power applied to these supplies.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifications for more details.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD.

Table 4.4. Thermal Characteristics

1. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 9 Via to top internal plane of PCB.

Figure 7.1. QFN40 Package Drawing

Table 7.1. QFN40 Package Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

5. Package external pad (epad) may have pin one chamfer.