DRV8874-Q1

Part: DRV8874 from Texas Instruments

Type: H-Bridge Motor Driver With Integrated Current Sense and Regulation

Key Specs:

• Operating supply voltage range: 4.5-V to 37-V
• DRV8874 R_DS(on): 200-mΩ (High-Side + Low-Side)
• DRV8874 Peak output current: 6-A Peak
• Ultra low-power sleep mode quiescent current: <1- μ A @ V_VM = 24-V, T_J = 25°C

Features:

• N-channel H-bridge motor driver
• Drives one bidirectional brushed DC motor
• Drives two unidirectional brushed DC motors
• Drives other resistive and inductive loads
• Pin to pin R_DS(on) variants (DRV8874, DRV8876)
• High output current capability
• Integrated current sensing and regulation
• Proportional current output (IPROPI)
• Selectable current regulation (IMODE): Cycle-by-cycle or fixed off time
• Selectable input control modes (PMODE): PH/EN and PWM H-bridge control modes, Independent half-bridge control mode
• Supports 1.8-V, 3.3-V, and 5-V logic inputs
• Ultra low-power sleep mode
• Spread spectrum clocking for low electromagnetic interference (EMI)
• Integrated protection features: Undervoltage lockout (UVLO), Charge pump undervoltage (CPUV), Overcurrent protection (OCP), Thermal shutdown (TSD), Automatic fault recovery, Fault indicator pin (nFAULT)

Applications:

• Brushed DC motors
• Major and small home appliances
• Vacuum, humanoid, and toy robotics
• Printers and scanners
• Smart meters
• ATMs, currency counters, and EPOS
• Servo motors and actuators

Package:

• HTSSOP (16): 5.00 mm × 4.40 mm

• N-channel H-bridge motor driver
  • Drives one bidirectional brushed DC motor
  • Two unidirectional brushed DC motors
  • Other resistive and inductive loads
• 4.5-V to 37-V operating supply voltage range
• Pin to pin R_DS(on) variants
  • DRV8874: 200-mΩ (High-Side + Low-Side)
  • DRV8876: 700-m Ω (High-Side + Low-Side)
• High output current capability
  • DRV8874: 6-A Peak
  • DRV8876: 3.5-A Peak
• Integrated current sensing and regulation
• Proportional current output (IPROPI)
• Selectable current regulation (IMODE)
  • Cycle-by-cycle or fixed off time
• Selectable input control modes (PMODE)
  • PH/EN and PWM H-bridge control modes
  • Independent half-bridge control mode
• Supports 1.8-V, 3.3-V, and 5-V logic inputs
• Ultra low-power sleep mode
  • <1- μ A @ V_VM = 24-V, T_J = 25°C
• Spread spectrum clocking for low electromagnetic interference (EMI)
• Integrated protection features
  • Undervoltage lockout (UVLO)
  • Charge pump undervoltage (CPUV)
  • Overcurrent protection (OCP)
    • Automatic retry or outputs latched off (IMODE)
  • Thermal shutdown (TSD)
  • Automatic fault recovery
  • Fault indicator pin (nFAULT)

• Brushed DC motors
• Major and small home appliances
• Vacuum, humanoid, and toy robotics
• Printers and scanners
• Smart meters
• ATMs, currency counters, and EPOS
• Servo motors and actuators

3 Description

The DRV8874 is an integrated motor driver with Nchannel H-bridge, charge pump, current sensing and proportional output, current regulation, and protection circuitry. The charge pump improves efficiency by supporting N-channel MOSFET half bridges and 100% duty cycle driving. The family of devices come in pin-to-pin R_DS(on) variants to support different loads with minimal design changes.

An internal current mirror architecture on the IPROPI pin implements current sensing and regulation. This eliminates the need for a large power shunt resistor, saving board area and reducing system cost. The IPROPI current-sense output allows a microcontroller to detect motor stall or changes in load conditions. Using the external voltage reference pin, VREF, these devices can regulate the motor current during start-up and high-load events without interaction from a microcontroller.

A low-power sleep mode achieves ultra-low quiescent current draw by shutting down most of the internal circuitry. Internal protection features include supply undervoltage lockout, charge pump undervoltage, output overcurrent, and device overtemperature. Fault conditions are indicated on nFAULT.

View our full portfolio of brushed motor drivers on ti.com.

Device Information (1)

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

5 Pin Configuration and Functions

DRV8874 PWP Package 16-Pin HTSSOP With Exposed Thermal Pad Top View

Pin Functions

• NAME
• CPH
• CPL
• EN/IN1
• GND
• IMODE
• IPROPI
• nFAULT
• nSLEEP
• OUT1
• OUT2
• PGND
• PH/IN2
• PMODE
• VCP
• VM
• VREF
• PAD

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1)

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

6.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)

(1) Power dissipation and thermal limits must be observed

⁽²⁾ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance.

6.4 Thermal Information

⁽¹⁾ For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

4.5 V ≤ VVM ≤ 37 V, –40°C ≤ T^J ≤ 150°C (unless otherwise noted)

Electrical Characteristics (continued)

4.5 V ≤ VVM ≤ 37 V, –40°C ≤ T^J ≤ 150°C (unless otherwise noted)

⁽¹⁾ At low currents, the IPROPI output has a fixed offset error with respect to the IOUT current through the low-side power MOSFETs.

Figure 1. Timing Parameter Diagram

6.6 Typical Characteristics

7 Detailed Description

7.1 Overview

The DRV887x family of devices are brushed DC motor drivers that operate from 4.5 to 37-V supporting a wide range of output load currents for various types of motors and loads. The devices integrate an H-bridge output power stage that can be operated in different control modes set by the PMODE pin setting. This allows for driving a single bidirectional brushed DC motor, two unidirectional brushed DC motors, or other output load configurations. The devices integrate a charge pump regulator to support more efficient high-side N-channel MOSFETs and 100% duty cycle operation. The devices operate from a single power supply input (VM) which can be directly connected to a battery or DC voltage supply. The nSLEEP pin provides an ultra-low power mode to minimize current draw during system inactivity.

The DRV887x family of devices also integrate current sense output using current mirrors on the low-side power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the MOSFETs. This current can be converted to a proportional voltage using an external resistor (R_IPROPI). The integrated current sensing allows the DRV887x devices to limit the output current with a fixed off-time PWM chopping scheme and provide load information to the external controller to detect changes in load or stall conditions. The integrated current sensing outperforms traditional external shunt resistor sensing by providing current information even during the off-time slow decay recirculating period and removing the need for an external power shunt resistor. The off-time PWM current regulation level can be configured during motor operation through the VREF pin to limit the load current accordingly to the system demands.

A variety of integrated protection features protect the device in the case of a system fault. These include undervoltage lockout (UVLO), charge pump undervoltage (CPUV), overcurrent protection (OCP), and overtemperature shutdown (TSD). Fault conditions are indicated on the nFAULT pin.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 External Components

Table 1 lists the recommended external components for the device.

Table 1. Recommended External Components

7.3.2 Control Modes

The DRV887x family of devices provides three modes to support different control schemes with the EN/IN1 and PH/IN2 pins. The control mode is selected through the PMODE pin with either logic low, logic high, or setting the pin Hi-Z as shown in Table 2. The PMODE pin state is latched when the device is enabled through the nSLEEP pin. The PMODE state can be changed by taking the nSLEEP pin logic low, waiting the tSLEEP time, changing the PMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high.

Table 2. PMODE Functions

Figure 10. H-Bridge States

The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive modes. The device input pins can be powered before VM is applied with no issues. By default, the EN/IN1 and PH/IN2 pins have an internal pulldown resistor to ensure the outputs are Hi-Z if no inputs are present.

The sections below show the truth table for each control mode. Note that these tables do not take into account the internal current regulation feature. Additionally, the DRV887x family of devices automatically handles the dead-time generation when switching between the high-side and low-side MOSFET of a half-bridge.

Figure 10 describes the naming and configuration for the various H-bridge states.

7.3.2.1 PH/EN Control Mode (PMODE = Logic Low)

When the PMODE pin is logic low on power up, the device is latched into PH/EN mode. PH/EN mode allows for the H-bridge to be controlled with a speed and direction type of interface. The truth table for PH/EN mode is shown in Table 3.

nSLEEP EN PH OUT1 OUT2 DESCRIPTION 0 X X Hi-Z Hi-Z Sleep, (H-Bridge Hi-Z) 1 0 X L L Brake, (Low-Side Slow Decay) 1 1 0 L H Reverse (OUT2 → OUT1) 1 1 1 H L Forward (OUT1 → OUT2)

Table 3. PH/EN Control Mode

7.3.2.2 PWM Control Mode (PMODE = Logic High)

When the PMODE pin is logic high on power up, the device is latched into PWM mode. PWM mode allows for the H-bridge to enter the Hi-Z state without taking the nSLEEP pin logic low. The truth table for PWM mode is shown in Table 4.

Table 4. PWM Control Mode

7.3.2.3 Independent Half-Bridge Control Mode (PMODE = Hi-Z)

When the PMODE pin is Hi-Z on power up, the device is latched into independent half-bridge control mode. This mode allows for each half-bridge to be directly controlled in order to support high-side slow decay or driving two independent loads. The truth table for independent half-bridge mode is shown in Table 5.

In independent half-bridge control mode, current sensing and feedback are still available, but the internal current regulation is disabled since each half-bridge is operating independently. Additionally, if both low-side MOSFETs are conducting current at the same time, the IPROPI scaled output will be the sum of the currents. See Current Sense and Regulation for more information.

Table 5. Independent Half-Bridge Control Mode

11

7.3.3 Current Sense and Regulation

The DRV887x family of devices integrate current sensing, regulation, and feedback. These features allow for the device to sense the output current without an external sense resistor or sense circuitry reducing system size, cost, and complexity. This also allows for the devices to limit the output current in the case of motor stall or high torque events and give detailed feedback to the controller about the load current through a current proportional output.

7.3.3.1 Current Sensing

The IPROPI pin outputs an analog current proportional to the current flowing through the low-side power MOSFETs in the H-bridge scaled by A_IPROPI . The IPROPI output current can be calculated by Equation 1. The I_LSx in Equation 1 is only valid when the current flows from drain to source in the low-side MOSFET. If current flows from source to drain, the value of I_LSx for that channel is zero. For instance, if the bridge is in the brake, slow-decay state, then the current out of IPROPI is only proportional to the current in one of the low-side MOSFETs.

$I_PROPI(μ A) = (I_LS1 + I_LS2)(A) × A_IPROPI(μ A/A)$

$tag{1}$

The current is measured by an internal current mirror architecture that removes the needs for an external power sense resistor. Additionally, the current mirror architecture allows for the motor winding current to be sensed in both the drive and brake low-side slow-decay periods allowing for continuous current monitoring in typical bidirectional brushed DC motor applications. In coast mode, the current is freewheeling and cannot be sensed because it flows from source to drain. However, the current can be sampled by briefly reenabling the driver in either drive or slow-decay modes and measuring the current before switching back to coast mode again. In the case of independent PWM mode and both low-side MOSFETs are carrying current, the IPROPI output will be the sum of the two low-side MOSFET currents.

The IPROPI pin should be connected to an external resistor ( $R_{IPROPI}$ ) to ground in order to generate a proportional voltage ( $V_{IPROPI}$ ) on the IPROPI pin with the $I_{IPROPI}$ analog current output. This allows for the load current to be measured as the voltage drop across the $R_{IPROPI}$ resistor with a standard analog to digital converter (ADC). The $R_{IPROPI}$ resistor can be sized based on the expected load current in the application so that the full range of the controller ADC is utilized. Additionally, the DRV887x devices implement an internal IPROPI voltage clamp circuit to limit $V_{IPROPI}$ with respect to $V_{VREF}$ on the VREF pin and protect the external ADC in case of output overcurrent or unexpected high current events.

The corresponding IPROPI voltage to the output current can be calculated by Equation 2.

$V_IPROPI(V) = I_PROPI(A) × R_IPROPI(Ω)(2)


Copyright © 2017, Texas Instruments Incorporated

Figure 11. Integrated Current Sensing


The IPROPI output bandwidth is limited by the sense delay time (t_DELAY) of the DRV887x internal current sensing circuit. This time is the delay from the low-side MOSFET enable command to the IPROPI output being ready. If the device is alternating between drive and slow-decay (brake) in an H-bridge PWM pattern then the low-side MOSFET sensing the current is continuously on and the sense delay time has no impact to the IPROPI output.

7.3.3.2 Current Regulation

The DRV887x family of devices integrate current regulation using either a fixed off-time or cycle-by-cycle PWM current chopping scheme. The current chopping scheme is selectable through the IMODE quad-level input. This allows the devices to limit the output current in case of motor stall, high torque, or other high current load events.

The IMODE level can be set by leaving the pin floating (Hi-Z), connecting the pin to GND, or connecting a resistor between IMODE and GND. The IMODE pin state is latched when the device is enabled through the nSLEEP pin. The IMODE state can be changed by taking the nSLEEP pin logic low, waiting the t_SLEEP time, changing the IMODE pin input, and then enabling the device by taking the nSLEEP pin back logic high. The IMODE input is also used to select the device response to an overcurrent event. See more details in the Protection Circuits section.

The internal current regulation can be disabled by tying IPROPI to GND and setting the VREF pin voltage greater than GND (if current feedback is not required) or if current feedback is required, settingV_{VREF}$ and $R_{IPROPI}$ such that $V_{IPROPI}$ never reaches the $V_{VREF}$ threshold. In independent half-bridge control mode (PMODE = Hi-Z), the internal current regulation is automatically disabled since the outputs are operating independently and the current sense and regulation is shared between half-bridges.

Table 6. IMODE Functions

The current chopping threshold ( $I_{TRIP}$ ) is set through a combination of the VREF voltage ( $V_{VREF}$ ) and IPROPI output resistor ( $R_{IPROPI}$ ). This is done by comparing the voltage drop across the external $R_{IPROPI}$ resistor to $V_{VREF}$ with an internal comparator.

$I_TRIP(A) × A_IPROPI(μ A/A) = V_VREF(V) / R_IPROPI(Ω)$ (3)

For example, if $V_{VREF} = 2.5 \text{ V}$ , $R_{IPROPI} = 1500 \Omega$ , and $A_{IPROPI} = 455 \mu A/A$ , then $I_{TRIP}$ will be approximately 3.66 A.

When the $I_{TRIP}$ threshold is exceeded, the outputs will enter a current chopping mode according to the IMODE setting. The $I_{TRIP}$ comparator has both a blanking time ( $t_{BLK}$ ) and a deglitch time ( $t_{DEG}$ ). The internal blanking time helps to prevent voltage and current transients during output switching from effecting the current regulation. These transients may be caused by a capacitor inside the motor or on the connections to the motor terminals. The internal deglitch time ensures that transient conditions do not prematurely trigger the current regulation. In certain cases where the transient conditions are longer than the deglitch time, placing a 10-nF capacitor on the IPROPI pin, close to the DRV887x, will help filter the transients on IPROPI output so current regulation does not prematurely trigger. The capacitor value can be adjusted as needed, however large capacitor values may slow down the response time of the current regulation circuitry.

The $A_{ERR}$ parameter in the Electrical Characteristics table is the error associated with the $A_{IPROPI}$ gain. It indicates the combined effect of offset error added to the $I_{OUT}$ current and gain error.

7.3.3.2.1 Fixed Off-Time Current Chopping

In the fixed off-time mode, the H-bridge enters a brake/low-side slow decay state (both low-side MOSFETs ON) for $t_{OFF}$ duration after $l_{OUT}$ exceeds $l_{TRIP}$ . After $t_{OFF}$ the outputs are re-enabled according to the control inputs unless $l_{OUT}$ is still greater than $l_{TRIP}$ . If $l_{OUT}$ is still greater than $l_{TRIP}$ , the H-bridge will enter another period of brake/low-side slow decay for $t_{OFF}$ . If the state of the EN/IN1 or PH/IN2 control pin inputs changes during the $t_{OFF}$ time, the remainder of the $t_{OFF}time is ignored, and the outputs will again follow the inputs.


The fixed off-time mode allows for a simple current chopping scheme without involvement from the external controller. This is shown in Figure 12. Fixed off-time mode will support 100% duty cycle current regulation since the H-bridge automatically enables after the tOFF period and does not require a new control input edge on the EN/IN1 or PH/IN2 pins to reset the outputs.


Figure 12. Off-Time Current-Regulation

7.3.3.2.2 Cycle-By-Cycle Current Chopping

In cycle-by-cycle mode, the H-bridge enters a brake, low-side slow decay state (both low-side MOSFETs ON) after IOUT exceeds ITRIP until the next control input edge on the EN/IN1 or PH/IN2 pins. This allows for additional control of the current chopping scheme by the external controller. This is shown in Figure 13. Cycle-by-cycle mode will not support 100% duty cycle current regulation as a new control input edge is required to reset the outputs after the brake, low-side slow decay state has been entered.


Figure 13. Cycle-By-Cycle Current Regulation

In cycle-by-cycle mode, the device will also indicate whenever the H-bridge enters internal current chopping by pulling the nFAULT pin low. This can be used to determine when the device outputs will differ from the control inputs or the load has reached the ITRIP threshold. This is shown in Figure 14. nFAULT will be released whenever the next control input edge is received by the device and the outputs are reset.



Figure 14. Cycle-By-Cycle Current Regulation Where nFAULT Acts as Current Chopping Indicator

No device functionality is affected when the nFAULT pin is pulled low for the current chopping indicator. The nFAULT pin is only used as an indicator and the device will continue normal operation. To distinguish a device fault (outlined in the Protection Circuits section) from the current chopping indicator, the nFAULT pin can be compared with the control inputs. The current chopping indicator can only assert when the control inputs are commanding a forward or reverse drive state (Figure 10). If the nFAULT pin behavior deviates from the operation shown in Figure 14 then one of the following situations has occurred:

• If a device fault has occurred, then the nFAULT pin pulls low to indicate a fault condition rather than current chopping. Depending on the device fault, nFAULT may remain low even when the control inputs are commanding the high-Z or slow-decay states.
• When the control inputs transition from drive to slow decay, the nFAULT pin will go high for t_BLK then be pulled low again if I_OUT > I_TRIP. This may be caused by a PWM frequency or duty cycle on the control inputs with a off-time that is too short for the I_OUT current to decay below the I_TRIP threshold. Figure 15 shows an example of this condition. The condition I_OUT > I_TRIP can be viewed on an oscilloscope as V_IPROPI > V_REF.



Chan. 1 = EN Chan. 2 = nFAULT Chan. 3 = VREF Chan. 4 = IPROPI

Figure 15. nFAULT Pin When VIPROPI > VVREF with PH/EN Mode and PWM Signal on EN Pin


7.3.4 Protection Circuits

The DRV887x family of devices are fully protected against supply undervoltage, charge pump undervoltage, output overcurrent, and device overtemperature events.

7.3.4.1 VM Supply Undervoltage Lockout (UVLO)

If at any time the supply voltage on the VM pin falls below the undervoltage lockout threshold voltage (V_{UVLO}$ ), all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The charge pump is disabled in this condition. Normal operation will resume when the undervoltage condition is removed and VM rises above the $V_{UVLO}$ threshold.

7.3.4.2 VCP Charge Pump Undervoltage Lockout (CPUV)

If at any time the charge pump voltage on the VCP pin falls below the undervoltage lockout threshold voltage $(V_{CPUV})$ , all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. Normal operation will resume when the undervoltage condition is removed and VCP rises above the $V_{CPUV}$ threshold.

7.3.4.3 OUTx Overcurrent Protection (OCP)

An analog current limit circuit on each MOSFET limits the peak current out of the device even in hard short circuit events.

If the output current exceeds the overcurrent threshold, $I_{OCP}$ , for longer than $t_{OCP}$ , all MOSFETs in the H-bridge will be disabled and the nFAULT pin driven low. The overcurrent response can be configured through the IMODE pin as shown in Table 6.

In automatic retry mode, the MOSFETs will be disabled and nFAULT pin driven low for a duration of t_RETRY. After t_RETRY, the MOSFETs are re-enabled according to the state of the EN/IN1 and PH/IN2 pins. If the overcurrent condition is still present, the cycle repeats; otherwise normal device operation resumes.

In latched off mode, the MOSFETs will remain disabled and nFAULT pin driven low until the device is reset through either the nSLEEP pin or by removing the VM power supply.

In Independent Half-Bridge Control Mode (PMODE = Hi-Z), the OCP behavior is slightly modified. If an overcurrent event is detected, only the corresponding half-bridge will be disabled and the nFAULT pin driven low. The other half-bridge will continue normal operation. This allows for the device to manage independent fault events when driving independent loads. If an overcurrent event is detected in both half-bridges, both half-bridges will be disabled and the nFAULT pin driven low. In automatic retry mode, both half-bridges share the same overcurrent retry timer. If an overcurrent event occurs first in one half-bridge and then later in the secondary half-bridge, but before $t_{RETRY}$ has expired, the retry timer for the first half-bridge will be reset to $t_{RETRY}$ and both half-bridges will enable again after the retry timer expires.

7.3.4.4 Thermal Shutdown (TSD)

If the die temperature exceeds the overtemperature limit $T_{TSD}$ , all MOSFET in the H-bridge will be disabled and the nFAULT pin driven low. Normal operation will resume when the overtemperature condition is removed and the die temperature drops below the $T_{TSD}$ threshold.

7.3.4.5 Fault Condition Summary

Table 7. Fault Condition Summary

7.3.5 Pin Diagrams

7.3.5.1 Logic-Level Inputs

Figure 16 shows the input structure for the logic-level input pins EN/IN1, PH/IN2, and nSLEEP.


Figure 16. Logic-Level Input

7.3.5.2 Tri-Level Inputs

Figure 17 shows the input structure for the tri-level input pin PMODE.


Figure 17. PMODE Tri-Level Input

7.3.5.3 Quad-Level Inputs

Figure 18 shows the input structure for the quad-level input pin IMODE.


Figure 18. Quad-Level Input

7.4 Device Functional Modes

The DRV887x family of devices have several different modes of operation depending on the system inputs.

7.4.1 Active Mode

After the supply voltage on the VM pin has crossed the undervoltage thresholdV_{UVLO}$ , the nSLEEP pin is logic high, and $t_{WAKE}has elapsed, the device enters its active mode. In this mode, the H-bridge, charge pump, and internal logic are active and the device is ready to receive inputs. The input control mode (PMODE) and current control modes (IMODE) will be latched when the device enters active mode.


Device Functional Modes (continued)

7.4.2 Low-Power Sleep Mode

The DRV887x family of devices support a low power mode to reduce current consumption from the VM pin when the driver is not active. This mode is entered by setting the nSLEEP pin logic low and waiting for tSLEEP to elapse. In sleep mode, the H-bridge, charge pump, internal 5-V regulator, and internal logic are disabled. The device relies on a weak pulldown to ensure all of the internal MOSFETs remain disabled. The device will not respond to any inputs besides nSLEEP while in low-power sleep mode.

7.4.3 Fault Mode

The DRV887x family of devices enter a fault mode when a fault is encountered. This is utilized to protect the device and the output load. The device behavior in the fault mode is described in Table 7 and depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is met.


8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV887x family of devices can be used in a variety of applications that require either a half-bridge or H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids, and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two half-bridge drivers.

8.2 Typical Application

8.2.1 Primary Application

In the primary application example, the device is configured to drive a bidirectional current through an external load (such as a brushed DC motor) using an H-bridge configuration. The H-bridge polarity and duty cycle are controlled with a PWM and IO resource from the external controller to the EN/IN1 and PH/IN2 pins. The device is configured for the PH/EN control mode by tying the PMODE pin to GND. The current limit threshold (I_TRIP) is generated with an external resistor divider from the control logic supply voltage (V_CC). The device is configured for the fixed off-time current regulation scheme by tying the IMODE pin to GND. The load current is monitored with an ADC from the controller to detect the voltage across R_IPROPI.


Figure 19. Typical Application Schematic


Typical Application (continued)

8.2.1.1 Design Requirements

Table 8. Design Parameters

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Current Sense and Regulation

The DRV887x family of devices provide integrated regulation and sensing out the output current.

The current sense feedback is configured by scaling the RIPROPI resistor to properly sense the scaled down output current from IPROPI within the dynamic voltage range of the controller ADC. An example of this is shown.R_IPROPI ≤ V_ADC / (I_TRIP × A_IPROPI) tag{4}$

$R_IPROPI = 5.5 kΩ ≤ 2.5 V / (1 A x 455 μA/A)$ (5)

If VADC = 2.5 V, ITRIP = 1 A, and AIPROPI = 455 μA/A then to maximize the dynamic IPROPI voltage range an RIPROPI of approximately 5.5 kΩ should be selected.

The accuracy tolerance of RIPROPI can be selected based on the application requirements. 10%, 5%, 1%, 0.1% are all valid tolerance values. The typical recommendation is 1% for best tradeoff between performance and cost.

The output current regulation trip point (ITRIP) is configured with a combination of VREF and RIPROPI. Since RIPROPI was previously calculated and AIPROPI is a constant, all the remains is to calculate VREF.

$V_REF = R_IPROPI × (I_TRIP × A_IPROPI) tag{6}$

$V_REF = 2.5 V = 5.5 kΩ x (1 A x 455 μA/A) tag{7}$

If RIPROPI = 5.5 kΩ, ITRIP = 1 A, and AIPROPI = 455 μA/A then VREF should be set to 2.5 V.

VREF can be generated with a simple resistor divider (RREF1 and RREF2) from the controller supply voltage. The resistor sizing can be achieved by selecting a value for RREF1 and calculating the required value for RREF2.

8.2.1.2.2 Power Dissipation and Output Current Capability

The output current and power dissipation capabilities of the device are heavily dependent on the PCB design and external system conditions. This section provides some guidelines for calculating these values.

Total power dissipation for the device is composed of three main components. These are the quiescent supply current dissipation, the power MOSFET switching losses. and the power MOSFET RDS(on) (conduction) losses. While other factors may contribute additional power losses, these other items are typically insignificant compared to the three main items.

$P_TOT = P_VM + P_SW + P_RDS tag{8}PVM can be calculated from the nominal supply voltage (VM) and the IVM active mode current specification.

P_VM = V_M × I_VM tag{9}$

$P_VM = 0.096 W = 24 V × 4 mA$ (10)

$P_{SW}$ can be calculated from the nominal supply voltage ( $V_M$ ), average output current ( $I_{RMS}$ ), switching frequency ( $f_{PWM}$ ) and the device output rise ( $t_{RISE}$ ) and fall ( $t_{FALL}$ ) time specifications.

$P_SW = P_{SW RISE} + P_{SW FALL}$ (11)

$P_{SW RISE} = 0.5 × V_M × I_RMS × t_RISE × f_PWM$ (12)

$P_{SW FALL} = 0.5 × V_M × I_RMS × t_FALL × f_PWM$ (13)

$P_{SW RISE} = 0.018 W = 0.5 × 24 V × 0.5 A × 150 ns × 20 kHz$ (14)

$P_{SW FALL} = 0.018 W = 0.5 × 24 V × 0.5 A × 150 ns × 20 kHz$ (15)

$P_SW = 0.036 W = 0.018 W + 0.018 W$ (16)

$P_{\text{RDS}}$ can be calculated from the device $R_{\text{DS(on)}}$ and average output current ( $I_{\text{RMS}})$

$P_RDS = I_RMS² x (R_DS(ON)HS + R_DS(ON)LS)$ (17)

It should be noted that $R_{DS(ON)}$ has a strong correlation with the device temperature. A curve showing the normalized $R_{DS(on)}$ with temperature can be found in the Typical Characteristics curves. Assuming a device temperature of 85 °C it can be expected that $R_{DS(on)}$ will see an increase of ~1.25 based on the normalized temperature data.

$P_RDS = 0.0625 W = (0.5 A)² x (100 mΩ x 1.25 + 100 mΩ x 1.25)$ (18)

By adding together the different power dissipation components it can be verified that the expected power dissipation and device junction temperature is within design targets.

$P_TOT = P_VM + P_SW + P_RDS$ (19)

$P_TOT = 0.194 W = 0.096 W + 0.036 W + 0.0625 W$ (20)

The device junction temperature can be calculated with the $P_{TOT}$ , device ambient temperature ( $T_A$ ), and package thermal resistance ( $R_{\theta JA}$ ). The value for $R_{\theta JA}$ is heavily dependent on the PCB design and copper heat sinking around the device.

$T_J = (P_TOT × R_{θ JA}) + T_A tag{21}$

$T₁ = 92^°C = (0.194 W x 35 °C/W) + 85^°C$ (22)

It should be ensured that the device junction temperature is within the specified operating region. Other methods exist for verifying the device junction temperature depending on the measurements available.

Additional information on motor driver current ratings and power dissipation can be found in Thermal Performance and Related Documentation.

8.2.1.2.3 Thermal Performance

The datasheet-specified junction-to-ambient thermal resistance, $R_{\theta JA}, is primarily useful for comparing various drivers or approximating thermal performance. However, the actual system performance may be better or worse than this value depending on PCB stackup, routing, number of vias, and copper area around the thermal pad. The length of time the driver drives a particular current will also impact power dissipation and thermal performance. This section considers how to design for steady-state and transient thermal conditions.

The data in this section was simulated using the following criteria:

• 2-layer PCB, standard FR4, 1-oz (35 mm copper thickness) or 2-oz copper thickness.
  • Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation.
  • Bottom layer: ground plane thermally connected through vias under the thermal pad for DRV887x. Bottom layer copper area varies with top copper area. Thermal vias are only present under the thermal pad (grid pattern with 1.2mm spacing).
• 4-layer PCB, standard FR4. Outer planes are 1-oz (35 mm copper thickness) or 2-oz copper thickness.
  • Top layer: DRV887x HTSSOP package footprint and copper plane heatsink. Top layer copper area is varied in simulation. Inner planes were kept at 1-oz.
  • Mid layer 1: GND plane thermally connected to DRV887x thermal pad through vias. The area of the ground plane is 74.2 mm x 74.2 mm.
  • Mid layer 2: power plane, no thermal connection.


• Bottom layer: signal layer with small copper pad underneath DRV887x and thermally connected through via stitching from the TOP and internal GND planes. Bottom layer thermal pad is the same size as the package (5 mm x 4.4 mm). Bottom pad size remains constant as top copper plane is varied. Thermal vias are only present under the thermal pad (grid pattern with 1.2mm spacing).

Figure 20 shows an example of the simulated board for the HTSSOP package. Table 9 shows the dimensions of the board that were varied for each simulation.


Figure 20. HTSSOP PCB model top layer

Table 9. Dimension A for 16-pin PWP package

8.2.1.2.3.1 Steady-State Thermal Performance

"Steady-state" conditions assume that the motor driver operates with a constant RMS current over a long period of time. Figure 21, Figure 22, Figure 23, and Figure 24 show how RθJA and ΨJB (junction-to-board characterization parameter) change depending on copper area, copper thickness, and number of layers of the PCB for the HTSSOP package. More copper area, more layers, and thicker copper planes decrease RθJA and ΨJB, which indicate better thermal performance from the PCB layout.



8.2.1.2.3.2 Transient Thermal Performance

The motor driver may experience different transient driving conditions that cause large currents to flow for a short duration of time. These may include

• Motor start-up when the rotor is not yet spinning at full speed.
• Fault conditions when there is a supply or ground short to one of the motor outputs, and the device goes into and out of overcurrent protection.
• Briefly energizing a motor or solenoid for a limited time, then de-energizing.

For these transient cases, the duration of drive time is another factor that impacts thermal performance. In transient cases, the thermal impedance parameterZ_{\theta JA}denotes the junction-to-ambient thermal performance. Figure 25 and Figure 26 show the simulated thermal impedances for 1-oz and 2-oz copper layouts for the HTSSOP package. These graphs indicate better thermal performance with short current pulses. For short periods of drive time, the device die size and package dominates the thermal performance. For longer drive pulses, board layout has a more significant impact on thermal performance. Both graphs show the curves for thermal impedance split due to number of layers and copper area as the duration of the drive pulse duration increases. Long pulses can be considered steady-state performance.



Figure 25. HTSSOP package junction-to-ambient thermal impedance for 1-oz copper layouts


Figure 26. HTSSOP package Junction-to-ambient thermal impedance for 2-oz copper layouts


8.2.1.3 Application Curves




8.2.2 Alternative Application

In the alternative application example, the device is configured to drive a unidirectional current through two external loads (such as two brushed DC motors) using a dual half-bridge configuration. The duty cycle of each half-bridge is controlled with a PWM resource from the external controller to the EN/IN1 and PH/IN2 pins. The device is configured for the independent half-bridge control mode by leaving the PMODE pin floating. Since the current regulation scheme is disabled in the independent half-bridge control mode, the VREF pin is tied to VCC. The combined load current is monitored with an ADC from the controller to detect the voltage across RIPROPI.


Figure 33. Typical Application Schematic


8.2.2.1 Design Requirements

Table 10. Design Parameters

8.2.2.2 Detailed Design Procedure

Refer to the Primary Application Detailed Design Procedure section for a detailed design procedure example. The majority of the design concepts apply to the alternative application example. A few changes to the procedure are outlined below.

8.2.2.2.1 Current Sense and Regulation

In the alternative application for two half-bridge loads, the IPROPI output will be the combination of the two outputs currents. The current sense feedback resistor RIPROPI should be scaled appropriately to stay within the dynamic voltage range of the controller ADC. An example of this is shownR_IPROPI ≤ftarrow V_ADC / ((I_PEAK1 + I_PEAK2) × A_IPROPI)$ (23)

$R_IPROPI = 4.8 kΩ <= 3.3 V / ((1 A + 0.5 A) × 455 μA/A)$ (24)

If VADC = 3.3 V, IPEAK1 = 1 A, IPEAK2 = 0.5 A, and AIPROPI = then to maximize the dynamic IPROPI voltage range an RIPROPI of approximately 4.8 kΩ should be selected.

The accuracy tolerance of RIPROPI can be selected based on the application requirements. 10%, 5%, 1%, 0.1% are all valid tolerance values. The typical recommendation is 1% for best tradeoff between performance and cost.

In independent half-bridge mode, the internal current regulation of the device is disabled. VREF can be set directly to the supply reference for the controller ADC.

8.2.2.3 Application Curves

9 Power Supply Recommendations

9.1 Bulk Capacitance

Having appropriate local bulk capacitance is an important factor in motor drive system design. Having more bulk capacitance is generally beneficial, while the disadvantages are increased cost and physical size.

The amount of local bulk capacitance needed depends on a variety of factors, including:

• The highest current required by the motor or load
• The capacitance of the power supply and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple of the system
• The motor braking method (if applicable)

The inductance between the power supply and motor drive system limits how the rate current can change from the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied.

The data sheet generally provides a recommended minimum value, but system level testing is required to determine the appropriately sized bulk capacitor.

Figure 36. System Supply Parasitics Example

10 Layout

10.1 Layout Guidelines

Since the DRV887x family of devices are integrated power MOSFETs device capable of driving high current, careful attention should be paid to the layout design and external component placement. Some design and layout guidelines are provided below.

• Low ESR ceramic capacitors should be utilized for the VM to GND bypass capacitor, the VCP to VM charge pump storage capacitor, and the charge pump flying capacitor. X5R and X7R types are recommended.
• The VM power supply and VCP, CPH, CPL charge pump capacitors should be placed as close to the device as possible to minimize the loop inductance.
• The VM power supply bulk capacitor can be of ceramic or electrolytic type, but should also be placed as close as possible to the device to minimize the loop inductance.
• VM, OUT1, OUT2, and PGND carry the high current from the power supply to the outputs and back to ground. Thick metal routing should be utilized for these traces as is feasible.
• PGND and GND should connect together directly on the PCB ground plane. They are not intended to be isolated from each other.
• The device thermal pad should be attached to the PCB top layer ground plane and internal ground plane (when available) through thermal vias to maximize the PCB heat sinking.
• A recommended land pattern for the thermal vias is provided in the package drawing section.
• The copper plane area attached to the thermal pad should be maximized to ensure optimal heat sinking.

10.2 Layout Example

10.2.1 HTSSOP Layout Example

Figure 37. HTSSOP (PWP) Example Layout

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
• Texas Instruments, Motor Drives Layout Guide application report
• Texas Instruments, DRV8874 Evaluation Module (EVM) tool folder

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

32

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 10-Nov-2025

PACKAGING INFORMATION

⁽¹⁾ Status: For more details on status, see our product life cycle.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device.

**Important Information and Disclaimer:**The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF DRV8874 :

⁽²⁾ Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

⁽³⁾ RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

⁽⁴⁾ Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

⁽⁵⁾ MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

⁽⁶⁾ Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

DRV8874 PWP Package 16-Pin HTSSOP With Exposed Thermal Pad Top View

Pin Functions

• NAME
• CPH
• CPL
• EN/IN1
• GND
• IMODE
• IPROPI
• nFAULT
• nSLEEP
• OUT1
• OUT2
• PGND
• PH/IN2
• PMODE
• VCP
• VM
• VREF
• PAD

4.5 V ≤ VVM ≤ 37 V, –40°C ≤ T^J ≤ 150°C (unless otherwise noted)

over operating temperature range (unless otherwise noted)(1)

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

over operating temperature range (unless otherwise noted)

(1) Power dissipation and thermal limits must be observed

⁽²⁾ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ± 500 V may actually have higher performance.