DRV8434A
DRV8434S Stepper Driver With Integrated Current Sense, 1/256 Microstepping, SPI Interface, Smart Tune Technology and Stall Detection
Manufacturer
Texas Instruments
Category
Integrated Circuits (ICs)
Overview
Part: DRV8434S Stepper Driver from Texas Instruments
Type: PWM Microstepping Stepper Motor Driver
Key Specs:
- Operating Supply Voltage Range: 4.5 to 48-V
- Low RDS(ON): 330 mΩ HS + LS at 24 V, 25°C
- High Current Capacity: 2.5 A Full-Scale, 1.8 A rms
- Microstepping Indexer: Up to 1/256
- Full-Scale Current Accuracy: ±4%
- Low-Current Sleep Mode: 2 μA
- Logic Inputs Support: 1.8 V, 3.3 V, 5.0 V
- Configurable Off-Time PWM Chopping: 7-μs, 16-μs, 24-μs, or 32-μs
Features:
- SPI Interface with STEP/DIR pins
- Integrated Current Sense Functionality (No Sense Resistors Required)
- Smart tune, slow, and mixed decay options
- TRQ_DAC bits to scale full-scale current
- Daisy Chain support with SPI
- Spread spectrum clocking for low EMI
- Small Package and Footprint
- VM Undervoltage Lockout (UVLO)
- Charge Pump Undervoltage (CPUV)
- Overcurrent Protection (OCP)
- Sensorless stall detection
- Open Load Detection (OL)
- Overtemperature Warning (OTW)
- Thermal Shutdown (OTSD)
- Fault Condition Output (nFAULT)
Applications:
- Printers and Scanners
- ATM and Money Handling Machines
- Textile Machines
- Stage Lighting Equipment
- Office and Home Automation
- Factory Automation and Robotics
- Medical Applications
- 3D Printers
Package:
- HTSSOP (28): 9.7mm x 4.4mm
- VQFN (24): 4mm x 4mm
Features
- PWM Microstepping Stepper Motor Driver
- SPI Interface with STEP/DIR pins
- Up to 1/256 Microstepping Indexer
- Integrated Current Sense Functionality
- No Sense Resistors Required
- ±4% Full-Scale Current Accuracy
- Smart tune, slow, and mixed decay options
- 4.5 to 48-V Operating Supply Voltage Range
- Low RDS(ON): 330 mΩ HS + LS at 24 V, 25°C
- High Current Capacity: 2.5 A Full-Scale, 1.8 A rms
- TRQ_DAC bits to scale full-scale current
- Configurable Off-Time PWM Chopping – 7-μs, 16-μs, 24-μs, or 32-μs
- Supports 1.8 V, 3.3 V, 5.0 V Logic Inputs
- Daisy Chain support with SPI
- Low-Current Sleep Mode (2 μA)
- Spread spectrum clocking for low EMI
- Small Package and Footprint
- Protection Features
- VM Undervoltage Lockout (UVLO)
- Charge Pump Undervoltage (CPUV)
- Overcurrent Protection (OCP)
- Sensorless stall detection
- Open Load Detection (OL)
- Overtemperature Warning (OTW)
- Thermal Shutdown (OTSD)
- Fault Condition Output (nFAULT)
Applications
Pin Configuration
Figure 5-2. RGE Package 24-Pin VQFN with Exposed Thermal PAD Top View
5.1 Pin Functions
- NAME
- AOUT1
- AOUT2
- PGND
- BOUT2
- BOUT1
- CPH
- CPL
- DIR
- ENABLE
- DVDD
- GND
- VREF
- nSCS
- SCLK
- SDI
- SDO
- STEP
- VCP
- VM
- VSDO
- nFAULT
- NAME
- nSLEEP
- PAD
Electrical Characteristics
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (VM, DVDD) | ||||||
| IVM | VM operating supply current | ENABLE = 1, nSLEEP = 1, No motor load | 5 | 6.5 | mA | |
| IVMQ | VM sleep mode supply current | nSLEEP = 0 | 2 | 4 | μA | |
| tSLEEP | Sleep time | nSLEEP = 0 to sleep-mode | 120 | μs | ||
| tRESET | nSLEEP reset pulse | nSLEEP low to clear fault | 20 | 40 | μs | |
| tWAKE | Wake-up time | nSLEEP = 1 to output transition | 0.8 | 1.2 | ms | |
| tON | Turn-on time | VM > UVLO to output transition | 0.8 | 1.2 | ms | |
| tEN | Enable time | ENABLE = 0/1 to output transition | 5 | μs | ||
| VDVDD | Internal regulator voltage | No external load, 6V < VVM < 48V | 4.75 | 5 | 5.25 | V |
| CHARGE PUMP (VCP, CPH, CPL) | No external load, VVM = 4.5V | 4.2 | 4.35 | V | ||
| VVCP | VCP operating voltage | 6V < VVM < 48V | VVM + 5 | V | ||
| f(VCP) | Charge pump switching frequency LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP, nSCS, SCLK, SDI, ENABLE) | VVM > UVLO; nSLEEP = 1 | 360 | kHz | ||
| VIL | Input logic-low voltage | 0 | 0.6 | V | ||
| VIH | Input logic-high voltage | 1.5 | 5.5 | V | ||
| VHYS | Input logic hysteresis | 150 | mV | |||
| IIL1 | Input logic-low current (nSCS) | VIN = 0 V | 8 | 12 | μA | |
| IIL | Input logic-low current (other pins) | VIN = 0 V | –1 | 1 | μA | |
| IIH1 | Input logic-high current (nSCS) | VIN = DVDD | 500 | nA | ||
| IIH | Input logic-high current (other pins) PUSH-PULL OUTPUT (SDO) | VIN = 5 V | 100 | μA | ||
| RPD,SDO | Internal pull-down resistance | 5mA load, with respect to GND | 30 | 60 | Ω | |
| RPU,SDO | Internal pull-up resistance | 5mA load, with respect to VSDO | 30 | 60 | Ω | |
| ISDO | SDO Leakage Current CONTROL OUTPUTS (nFAULT) | SDO = VSDO and 0V | -1 | 1 | μA | |
| VOL | Output logic-low voltage | IO = 5 mA | 0.5 | V | ||
| IOH | Output logic-high leakage MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | –1 | 1 | μA | ||
| High-side FET on resistance | TJ = 25 °C, IO = -1 A | 165 | 200 | mΩ | ||
| RDS(ON) | TJ = 125 °C, IO = -1 A | 250 | 300 | mΩ | ||
| TJ = 150 °C, IO = -1 A | 280 | 350 | mΩ | |||
| TJ = 25 °C, IO = 1 A | 165 | 200 | mΩ | |||
| RDS(ON) | Low-side FET on resistance | TJ = 125 °C, IO = 1 A | 250 | 300 | mΩ | |
| TJ = 150 °C, IO = 1 A | 280 | 350 | mΩ | |||
| tSR | Output slew rate | VVM = 24 V, IO = 1 A, Between 10% and 90% | 240 | V/μs | ||
| PWM CURRENT CONTROL (VREF) | ||||||
| KV | Transimpedance gain | VREF = 3.3 V | 1.254 | 1.32 | 1.386 | V/A |
| IVREF | VREF leakage current | VREF = 3.3 V | 8.25 | μA |
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| tOFF | PWM off-time | TOFF = 00b | 7 | ||
| TOFF = 01b | 16 | ||||
| TOFF = 10b | 24 | ||||
| TOFF = 11b | 32 | ||||
| ΔITRIP | Current trip accuracy | 0.25 A < IO < 0.5 A | –12 | 12 | |
| 0. |
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | |
|---|---|---|---|
| Power supply voltage (VM) | –0.3 | 50 | V |
| Charge pump voltage (VCP, CPH) | –0.3 | VVM + 7 | V |
| Charge pump negative switching pin (CPL) | –0.3 | VVM | V |
| nSLEEP pin voltage (nSLEEP) | –0.3 | VVM | V |
| Internal regulator voltage (DVDD) | –0.3 | 5.75 | V |
| SDO output reference voltage (VSDO) | –0.3 | 5.75 | V |
| Control pin voltage (STEP, DIR, ENABLE, nFAULT, SDI, SDO, SCLK, nSCS) | –0.3 | 5.75 | V |
| Open drain output current (nFAULT) | 0 | 10 | mA |
| Reference input pin voltage (VREF) | –0.3 | 5.75 | V |
| Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) | –1 | VVM + 1 | V |
| Transient 100 ns phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) | –3 | VVM + 3 | V |
| Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2) | Internally Limited | A | |
| Operating ambient temperature, TA | –40 | 125 | °C |
| Operating junction temperature, TJ | –40 | 150 | °C |
| Storage temperature, Tstg | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VVM | Supply voltage range for normal (DC) operation | 4.5 | 48 | V |
| VI | Logic level input voltage | 0 | 5.5 | V |
| VVREF | VREF voltage | 0.05 | 3.3 | V |
| fSTEP | Applied STEP signal (STEP) | 0 | 500(1) | kHz |
| IFS | Motor full-scale current (xOUTx) | 0 | 2.5(2) | A |
| Irms | Motor RMS current (xOUTx) | 0 | 1.8(2) | A |
| TA | Operating ambient temperature | –40 | 125 | °C |
| TJ | Operating junction temperature | –40 | 150 | °C |
(1) STEP input can operate up to 500 kHz, but system bandwidth is limited by the motor load
(2) Power dissipation and thermal limits must be observed
6.4 Thermal Information
| THERMAL METRIC(1) | PWP (HTSSOP) | RGE (VQFN) | |
|---|---|---|---|
| 28 PINS | 24 PINS | ||
| RθJA | Junction-to-ambient thermal resistance | 29.7 | 39.0 |
| Rθ JC(top) | Junction-to-case (top) thermal resistance | 23.0 | 28.9 |
| RθJB | Junction-to-board thermal resistance | 9.3 | 16.0 |
| ψJT | Junction-to-top characterization parameter | 0.3 | 0.4 |
| ψJB | Junction-to-board characterization parameter | 9.2 | 15.9 |
| Rθ JC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 | 3.4 |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLIES (VM, DVDD) | ||||||
| IVM | VM operating supply current | ENABLE = 1, nSLEEP = 1, No motor load | 5 | 6.5 | mA | |
| IVMQ | VM sleep mode supply current | nSLEEP = 0 | 2 | 4 | μA | |
| tSLEEP | Sleep time | nSLEEP = 0 to sleep-mode | 120 | μs | ||
| tRESET | nSLEEP reset pulse | nSLEEP low to clear fault | 20 | 40 | μs | |
| tWAKE | Wake-up time | nSLEEP = 1 to output transition | 0.8 | 1.2 | ms | |
| tON | Turn-on time | VM > UVLO to output transition | 0.8 | 1.2 | ms | |
| tEN | Enable time | ENABLE = 0/1 to output transition | 5 | μs | ||
| VDVDD | Internal regulator voltage | No external load, 6V < VVM < 48V | 4.75 | 5 | 5.25 | V |
| CHARGE PUMP (VCP, CPH, CPL) | No external load, VVM = 4.5V | 4.2 | 4.35 | V | ||
| VVCP | VCP operating voltage | 6V < VVM < 48V | VVM + 5 | V | ||
| f(VCP) | Charge pump switching frequency LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP, nSCS, SCLK, SDI, ENABLE) | VVM > UVLO; nSLEEP = 1 | 360 | kHz | ||
| VIL | Input logic-low voltage | 0 | 0.6 | V | ||
| VIH | Input logic-high voltage | 1.5 | 5.5 | V | ||
| VHYS | Input logic hysteresis | 150 | mV | |||
| IIL1 | Input logic-low current (nSCS) | VIN = 0 V | 8 | 12 | μA | |
| IIL | Input logic-low current (other pins) | VIN = 0 V | –1 | 1 | μA | |
| IIH1 | Input logic-high current (nSCS) | VIN = DVDD | 500 | nA | ||
| IIH | Input logic-high current (other pins) PUSH-PULL OUTPUT (SDO) | VIN = 5 V | 100 | μA | ||
| RPD,SDO | Internal pull-down resistance | 5mA load, with respect to GND | 30 | 60 | Ω | |
| RPU,SDO | Internal pull-up resistance | 5mA load, with respect to VSDO | 30 | 60 | Ω | |
| ISDO | SDO Leakage Current CONTROL OUTPUTS (nFAULT) | SDO = VSDO and 0V | -1 | 1 | μA | |
| VOL | Output logic-low voltage | IO = 5 mA | 0.5 | V | ||
| IOH | Output logic-high leakage MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | –1 | 1 | μA | ||
| High-side FET on resistance | TJ = 25 °C, IO = -1 A | 165 | 200 | mΩ | ||
| RDS(ON) | TJ = 125 °C, IO = -1 A | 250 | 300 | mΩ | ||
| TJ = 150 °C, IO = -1 A | 280 | 350 | mΩ | |||
| TJ = 25 °C, IO = 1 A | 165 | 200 | mΩ | |||
| RDS(ON) | Low-side FET on resistance | TJ = 125 °C, IO = 1 A | 250 | 300 | mΩ | |
| TJ = 150 °C, IO = 1 A | 280 | 350 | mΩ | |||
| tSR | Output slew rate | VVM = 24 V, IO = 1 A, Between 10% and 90% | 240 | V/μs | ||
| PWM CURRENT CONTROL (VREF) | ||||||
| KV | Transimpedance gain | VREF = 3.3 V | 1.254 | 1.32 | 1.386 | V/A |
| IVREF | VREF leakage current | VREF = 3.3 V | 8.25 | μA |
Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| tOFF | PWM off-time | TOFF = 00b | 7 | ||
| TOFF = 01b | 16 | ||||
| TOFF = 10b | 24 | ||||
| TOFF = 11b | 32 | ||||
| ΔITRIP | Current trip accuracy | 0.25 A < IO < 0.5 A | –12 | 12 | |
| 0. |
Thermal Information
| THERMAL METRIC(1) | PWP (HTSSOP) | RGE (VQFN) | |
|---|---|---|---|
| 28 PINS | 24 PINS | ||
| RθJA | Junction-to-ambient thermal resistance | 29.7 | 39.0 |
| Rθ JC(top) | Junction-to-case (top) thermal resistance | 23.0 | 28.9 |
| RθJB | Junction-to-board thermal resistance | 9.3 | 16.0 |
| ψJT | Junction-to-top characterization parameter | 0.3 | 0.4 |
| ψJB | Junction-to-board characterization parameter | 9.2 | 15.9 |
| Rθ JC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 | 3.4 |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| DRV8434S | Texas Instruments | — |
| DRV8434SPWPR | Texas Instruments | 28-PowerTSSOP (0.173", 4.40mm Width) |
| DRV8434SPWPR.A | Texas Instruments | — |
| DRV8434SRGER | Texas Instruments | — |
| DRV8434SRGER.A | Texas Instruments | — |
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.
Get structured datasheet data via API
Get started free