CY8C5888

Part: Infineon (Cypress) PSoC 5LP: CY8C58LP Family

Type: Programmable System-on-Chip (PSoC)

Description: A true programmable embedded system-on-chip integrating configurable analog and digital peripherals, memory, and a 32-bit Arm Cortex-M3 microcontroller operating at up to 80 MHz, with up to 256 KB Flash and 64 KB RAM.

Operating Conditions:

• Supply voltage: 1.71 to 5.5 V
• Operating temperature: -40 to 105 °C
• Max clock frequency: 80 MHz

Absolute Maximum Ratings:

• Max supply voltage: null
• Max continuous current: null
• Max junction/storage temperature: 150 °C

Key Specs:

• CPU: 32-bit Arm Cortex-M3, up to 80 MHz
• Program Flash: Up to 256 KB, with cache and security features
• RAM: Up to 64 KB
• EEPROM: 2 KB
• DMA Controller: 24-channel
• ADC: Configurable 8- to 20-bit delta-sigma ADC, up to two 12-bit SAR ADCs
• DAC: Four 8-bit DACs
• I/O Pins: 46 to 72 I/O pins (up to 62 GPIOs)

Features:

• Ultra low power with industry's widest voltage range
• Programmable digital and analog peripherals enable custom functions
• Flexible routing of any analog or digital peripheral function to any pin
• CapSense® support, up to 62 sensors
• JTAG, SWD, SWV, and Traceport interfaces for programming, debug, and trace

Applications:

• Consumer applications
• Industrial applications
• Medical applications

Package:

• 68-pin QFN
• 100-pin TQFP
• 99-pin CSP

• Operating characteristics

• □ Voltage range: 1.71 to 5.5 V, up to 6 power domains

• □ Temperature range (ambient): -40 to 85 °C ^[1] Extended temperature parts: -40 to 105 °C

• □ DC to 80-MHz operation

• Power modes

• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz

• 2-μA sleep mode

• 300-nA hibernate mode with RAM retention

• Boost regulator from 0.5-V input up to 5-V output

• Performance

  • □ 32-bit Arm Cortex-M3 CPU, 32 interrupt inputs
  • 24-channel direct memory access (DMA) controller
  • 24-bit 64-tap fixed-point digital filter processor (DFB)
• • □ Up to 256 KB program flash, with cache and security features
  • □ Up to 32 KB additional flash for error correcting code (ECC)
  • □ Up to 64 KB RAM

• 2 KB EEPROM

• Digital peripherals

  • □ Four 16-bit timer, counter, and PWM (TCPWM) blocks

  • □ I²C, 1 Mbps bus speed

  • USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral interface (TID#10840032) using internal oscillator¹²¹

  • Full CAN 2.0b, 16 Rx, 8 Tx buffers

  • 20 to 24 universal digital blocks (UDB), programmable to create any number of functions: 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

    • I²C, UART, SPI, I2S, LIN 2.0 interfaces
    • Cyclic redundancy check (CRC)
    • · Pseudo random sequence (PRS) generators
    • · Quadrature decoders
    • · Gate-level logic functions

• Programmable clocking

  • □ 3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz
  • □ 4- to 25-MHz external crystal oscillator

• Internal PLL clock generation up to 80 MHz

• □ Low-power internal oscillator at 1, 33, and 100 kHz

• □ 32.768-kHz external watch crystal oscillator

• 12 clock dividers routable to any peripheral or I/O

• Analog peripherals

  • □ Configurable 8- to 20-bit delta-sigma ADC
  • □ Up to two 12-bit SAR ADCs
  • Four 8-bit DACs
  • Four comparators
  • Four opamps
  • Four programmable analog blocks, to create:
    • Programmable gain amplifier (PGA)
    • Transimpedance amplifier (TIA)
    • Mixer
    • Sample and hold circuit
  • □ CapSense^® support, up to 62 sensors
  • 1.024 V ±0.1% internal voltage reference

• Versatile I/O system

  • 46 to 72 I/O pins up to 62 general-purpose I/Os (GPIOs)

  • Up to eight performance I/O (SIO) pins

  • 25 mA current sink

  • · Programmable input threshold and output high voltages

  • · Can act as a general-purpose comparator

  • Hot swap capability and overvoltage tolerance

  • □ Two USBIO pins that can be used as GPIOs

  • □ Route any digital or analog peripheral to any GPIO □ LCD direct drive from any GPIO, up to 46 × 16 segments

  • CapSense support from any GPIO

  • 1.2-V to 5.5-V interface voltages, up to four power domains

• Programming, debug, and trace □ JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire viewer (SWV), and Traceport (5-wire) interfaces

  • Arm debug and trace modules embedded in the CPU core
  • Bootloader programming through I²C, SPI, UART, USB, and other interfaces

• Package options: 68-pin QFN, 100-pin TQFP, and 99-pin CSP

• Development support with free PSoC Creator™ tool

• □ Schematic and firmware design support

• □ Over 100 PSoC Components™ integrate multiple ICs and system interfaces into one PSoC. Components are free embedded ICs represented by icons. Drag and drop component icons to design systems in PSoC Creator.

• Includes free GCC compiler, supports Keil/Arm MDK

• Supports device programming and debugging

IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for high-current DACs (IDAC).

Opamp0out, Opamp1out, Opamp2out, Opamp3out. High current output of uncommitted opamp.^[7]

Extref0, Extref1. External reference input to the analog system. SAR0 EXTREF, SAR1 EXTREF. External references for SAR ADCs

Opamp0-, Opamp1-, Opamp2-, Opamp3-. Inverting input to uncommitted opamp.

Opamp0+, Opamp1+, Opamp2+, Opamp3+. Noninverting input to uncommitted opamp.

GPIO. Provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense. ^[7]

I2C0: SCL, I2C1: SCL. I²C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I²C SCL if wake from sleep is not required.

I2C0: SDA, I2C1: SDA. I²C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I²C SDA if wake from sleep is not required.

Ind. Inductor connection to boost pump.

kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin.

MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25-MHz crystal oscillator pin.

nTRST. Optional JTAG Test Reset programming and debug port connection to reset the JTAG connection.

SIO. Provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered.

SWDCK. SWD Clock programming and debug port connection.

SWDIO. SWD Input and Output programming and debug port connection.

TCK. JTAG Test Clock programming and debug port connection.

TDI. JTAG Test Data In programming and debug port connection.

TDO. JTAG Test Data Out programming and debug port connection.

TMS. JTAG Test Mode Select programming and debug port connection

TRACECLK. Cortex-M3 TRACEPORT connection, clocks TRACEDATA pins.

TRACEDATA[3:0]. Cortex-M3 TRACEPORT connections, output data.

SWV. SWV output.

USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB.

USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB.

VBOOST. Power sense connection to boost pump.

VBAT. Battery supply to boost pump.

VCCA. Output of the analog core regulator or the input to the analog core. Requires a 1uF capacitor to VSSA. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 26.

VCCD. Output of the digital core regulator or the input to the digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1uF capacitor to VSSD. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 26.

VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA.

VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA.

VSSA. Ground for all analog peripherals.

VSSB. Ground connection for boost pump.

VSSD. Ground for all digital logic and I/O pins.

VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to VDDA.

XRES. External reset pin. Active low with internal pull-up.

Note

7. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-84932 Rev. *O

Specifications are valid for –40 °C TA 105 °C and TJ 120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the Example Peripherals on page 40 for further explanation of PSoC Creator components.

Table 11-1. Absolute Maximum Ratings DC Specifications[14]

Notes

^14. Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

^15. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO VDDA.

^16. Meets or exceeds JEDEC Spec EIA/JESD78E IC Latch-up Test.