CLRC66302
Multi-Protocol NFC FrontendThe CLRC66302 is a multi-protocol nfc frontend from NXP Semiconductors. View the full CLRC66302 datasheet below including key specifications.
CLRC66302 shares its datasheet with CLRC66303, whose page lists every part number it covers.
Official CLRC66302 datasheet (PDF) — the source this page was extracted from.
Manufacturer
NXP SemiconductorsCategory
Multi-Protocol NFC Frontend
CLRC66302 Key Specifications
| Parameter | Value |
|---|---|
| Ambient Temperature Range High | 105 °C |
| Frequency | 13.56MHz |
| Frequency | 13.56 MHz |
| Height | 1 mm |
| Height - Seated (Max) | 1 mm |
| Interface | I2C, RS-232, SPI, UART |
| Interface | I2C, SPI, UART |
| Introduction Date | 2018-05-16 |
| Length | 5 mm |
| Lifecycle Status | Production (Last Updated: 1 month ago) |
| Max Frequency | 27.12 MHz |
| Max Junction Temperature (Tj) | 125 °C |
| Max Operating Temperature | 105 °C |
| Max Power Dissipation | 1.125 W |
| Max Supply Voltage | 5.5 V |
| Min Operating Temperature | -40 °C |
| Min Supply Voltage | 2.5 V |
| Mounting Type | Surface Mount |
| Nominal Supply Current | 17 mA |
| Nominal Supply Voltage (DC) | 5 V |
| Number of Terminals | 32 |
| Operating Temperature | -40°C ~ 105°C |
| Package / Case | 32-VFQFN Exposed Pad |
| Packaging | MouseReel |
| Packaging | Cut Tape |
| REACH SVHC | Unaffected |
| RoHS | Compliant |
| Schedule B | 8542390000, 8542390000|8542390000|8542390000|8542390000|8542390000 |
| Standard Pack Qty | 6000 |
| Standards | ISO 14443, ISO 15693, 18000-3, MIFARE, NFC |
| Supplier Device Package | 32-HVQFN (5x5) |
| Terminal Pitch | 500 µm |
| Type | RFID Reader |
| Supply Voltage | 2.5V ~ 5.5V |
| Width | 5 mm |
CLRC66302 Overview
Part: CLRC66303HNY — NXP Semiconductors
Type: High-Performance Multi-Protocol NFC Frontend (Reader/Writer IC)
Description: 2.5–5.5 V multi-protocol NFC frontend supporting ISO/IEC 14443A/B, MIFARE, FeliCa, ISO/IEC 15693 and ISO/IEC 18092 passive initiator, with SPI, I2C and UART host interfaces, a 512-byte FIFO and transfer speeds up to 848 kbit/s.
Operating Conditions:
- Supply voltage (VDD, TVDD): 2.5–5.5 V
- PVDD: 2.5–5.5 V (all host interfaces except I2C); 3.0–5.5 V when the I2C interface is used
- Operating ambient temperature: -40 to +105 °C (HVQFN32 package, still air, exposed pad soldered on a 4-layer JEDEC PCB)
- Maximum junction temperature (recommended): +125 °C
Absolute Maximum Ratings:
- Supply voltage (VDD, PVDD, TVDD): -0.5 to +6.0 V
- TVDD supply current (CLRC66303): 500 mA
- Input voltage on RXP/RXN: -0.5 to +2.0 V
- Total power dissipation: 1125 mW per package
- ESD: ±2000 V (HBM), ±500 V (CDM)
- Maximum junction temperature: +150 °C
- Storage temperature: -55 to +150 °C (no supply applied)
Key Specs:
- Supply current IDD: 17 mA typ, 20 mA max
- TVDD supply current: 180 mA typ, 350 mA max (recommended operation); 500 mA absolute limit
- Power-down current (PDOWN pin high): 8 nA typ, 40 nA max
- SPI up to 10 Mbit/s
- I2C up to 400 kBd (Fast mode) and 1000 kBd (Fast mode plus)
- UART up to 1228.8 kBd
- Typical read/write operating distance for ISO/IEC 14443A / MIFARE Classic: up to 12 cm (depends on antenna size and tuning)
- Crystal frequency 27.12 MHz with integrated PLL for the system clock
Features:
- Supports ISO/IEC 14443 type A and B, MIFARE Classic (hardware encryption), FeliCa, ISO/IEC 15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3
- P2P passive initiator mode per ISO/IEC 18092
- Low-Power Card Detection with a more flexible configuration (LPCD_OPTIONS register) than the CLRC66301/02
- 512-byte FIFO buffer
- Separate I2C interface for a secure access module (SAM)
- Power-saving modes: hard power-down, standby, low-power card detection
- Up to 8 free programmable input/output pins
- EMV contactless RF-level compliance achievable
- HVQFN32 with wettable flanks
Applications:
- Industrial
- Access control
- Gaming
Package:
- HVQFN32 (SOT617-1), 5 × 5 × 0.85 mm, 32 terminals plus central ground, wettable flanks, MSL2; CLRC66303HNY is delivered on a 6000-piece reel
- Other CLRC66303 option: VFBGA36 (SOT1985-1), 3.5 × 3.5 × 0.8 mm, 0.5 mm pitch
CLRC66302 Features
- Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property licensing rights
- High performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s
- Supports ISO/IEC 14443 type A, MIFARE Classic, ISO/IEC 14443 B and FeliCa reader modes
- P2P passive initiator mode in accordance with ISO/IEC 18092
- Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3/ EPC Class-1 HF
- Supports MIFARE Classic product encryption by hardware in read/write mode Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1 kB memory, MIFARE Classic with 4 kB memory, MIFARE DESFire EV1, MIFARE DESFire EV2 and MIFARE Plus ICs
- Low-Power Card Detection
- Compliance to EMV contactless protocol specification on RF level can be achieved
- Supported host interfaces:
- -SPI up to 10 Mbit/s
- -I 2 C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
- -RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage supply
- Separate I 2 C-bus interface for connection of a secure access module (SAM)
- FIFO buffer with size of 512 bytes for highest transaction performance
- Flexible and efficient power-saving modes including hard power down, standby and low-power card detection
- Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal
- 3.0 V to 5.5 V power supply (CLRC66301, CLRC66302) 2.5 V to 5.5 V power supply (CLRC66303)
- Up to 8 free programmable input/output pins
- Typical operating distance in read/write mode for communication to a ISO/IEC 14443 type A and MIFARE Classic card up to 12 cm, depending on the antenna size and tuning
- Two package options are available for the CLRC66303:
- HVQFN32: Package with wettable flanks easing the soldering process and quality control of soldered parts
- VFBGA36: Smallest package with optimized pin configuration for simple PCB layout
- The version CLRC66303 offers a more flexible configuration for Low-Power Card detection compared to the CLRC66301 and CLRC66302 with the new register LPCD_OPTIONS. In addition, the CLRC66303 offers new additional settings for the Load Protocol which fit very well to smaller antennas. The CLRC66303 is therefore the recommended version for new designs.
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
CLRC66302 Applications
- Industrial
- Access control
- Gaming
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
CLRC66302 Pin Configuration
Table 4. Pin description
| Pin | Symbol | Type | Description |
|---|---|---|---|
| 1 | TDO / OUT0 | O | test data output for boundary scan interface / general purpose output 0 |
| 2 | TDI / OUT1 | I/O | test data input boundary scan interface / general purpose output 1 |
| 3 | TMS / OUT2 | I/O | test mode select boundary scan interface / general purpose output 2 |
| 4 | TCK / OUT3 | I/O | test clock boundary scan interface / general purpose output 3 |
| 5 | SIGIN /OUT7 | I/O | Contactless communication interface output. / general purpose output 7 |
| 6 | SIGOUT | O | Contactless communication interface input. |
| 7 | DVDD | PWR | digital power supply buffer [1] |
| 8 | VDD | PWR | power supply |
| 9 | AVDD | PWR | analog power supply buffer [1] |
| 10 | AUX1 | O | auxiliary outputs: Pin is used for analog test signal |
| 11 | AUX2 | O | auxiliary outputs: Pin is used for analog test signal |
| 12 | RXP | I | receiver input pin for the received RF signal. |
| 13 | RXN | I | receiver input pin for the received RF signal. |
| 14 | VMID | PWR | internal receiver reference voltage [1] |
| 15 | TX2 | O | transmitter 2: delivers the modulated 13.56 MHz carrier |
| 16 | TVSS | PWR | transmitter ground, supplies the output stage of TX1, TX2 |
| 17 | TX1 | O | transmitter 1: delivers the modulated 13.56 MHz carrier |
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Table 4. Pin description ...continued
| Pin | Symbol | Type | Description |
|---|---|---|---|
| 18 | TVDD | PWR | transmitter voltage supply |
| 19 | XTAL1 | I | crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz) |
| 20 | XTAL2 | O | crystal oscillator output: output of the inverting amplifier of the oscillator |
| 21 | PDOWN | I | Power Down (RESET) |
| 22 | CLKOUT / OUT6 | O | clock output / general purpose output 6 |
| 23 | SCL | O | Serial Clock line |
| 24 | SDA | I/O | Serial Data Line |
| 25 | PVDD | PWR | pad power supply |
| 26 | IFSEL0 / OUT4 | I | host interface selection 0 / general purpose output 4 |
| 27 | IFSEL1 / OUT5 | I | host interface selection 1 / general purpose output 5 |
| 28 | IF0 | I/O | interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I 2 C, I 2 C-L |
| 29 | IF1 | I/O | interface pin, multifunction pin: Can be assigned to host interface SPI, I 2 C, I 2 C-L |
| 30 | IF2 | I/O | interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I 2 C, I 2 C-L |
| 31 | IF3 | I/O | interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, I 2 C, I 2 C-L |
| 32 | IRQ | O | interrupt request: output to signal an interrupt event |
| 33 | VSS | PWR | ground and heat sink connection |
CLRC66302 Recommended Operating Conditions
Exposure of the device to other conditions than specified in the Recommended Operating Conditions section for extended periods may affect device reliability.
Electrical parameters (minimum, typical and maximum) of the device are guaranteed only when it is used within the recommended operating conditions.
Table 250. Operating conditions CLRC66301, CLRC66302
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| V DD | supply voltage | 3.0 | 5.0 | 5.5 | V | |
| V DD(TVDD) | TVDD supply voltage | 3.0 | 5.0 | 5.5 | V | |
| V DD(PVDD) | PVDD supply voltage | all host interfaces | 3.0 | 5.0 | 5.5 | V |
| T j(max) | maximum junction temperature | - | - | - | +125 | °C |
| T amb | operating ambient temperature | in still air with exposed pin soldered on a 4 layer JEDEC PCB | -25 | +25 | +85 | °C |
| T stg | storage temperature | no supply voltage applied, relative humidity 45...75% | -45 | +25 | +125 | °C |
Table 251. Operating conditions CLRC66303
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| V DD | supply voltage | 2.5 | 5.0 | 5.5 | V | |
| V DD(TVDD) | TVDD supply voltage | 2.5 | 5.0 | 5.5 | V | |
| V DD(PVDD) | PVDD supply voltage | all host interfaces except I2C interface | 2.5 | 5.0 | 5.5 | V |
| V DD(PVDD) | all host interfaces incl. I2C interface | 3.0 | 5.0 | 5.5 | V | |
| T j(max) | maximum junction temperature | - | - | - | +125 | °C |
| T amb | operating ambient temperature | HVQFN32 package, in still air with exposed pin soldered on a 4 layer JEDEC PCB | -40 | +25 | +105 | °C |
| T amb | VFBGA36 package, in still air with exposed pin soldered on a 4 layer JEDEC PCB | -40 | +25 | +85 | °C | |
| T stg | storage temperature | no supply voltage applied, relative humidity 45...75% | -45 | +25 | +125 | °C |
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
CLRC66302 Thermal Information
| Symbol | Parameter | Conditions | Package | Typ | Unit |
|---|---|---|---|---|---|
| R th(j-a) | thermal resistance from junction to ambient | in still air with exposed pin soldered on a 4 layer JEDEC PCB | HVQFN32 | 40 | K/W |
CLRC66302 Typical Application
A typical application diagram using a complementary antenna connection to the CLRC663 is shown in the following figure.
The antenna tuning and RF part matching is described in the application note [1] and [2].
Figure 36. Typical application antenna circuit diagram
CLRC66302 Package Information
| OUTLINE VERSION | REFERENCES - IEC | REFERENCES - JEDEC | REFERENCES - JEITA | EUROPEAN PROJECTION | ISSUE DATE |
|---|---|---|---|---|---|
| SOT617-1 | - - - | MO-220 | - - - | 01-08-08 02-10-18 |
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
15.2 Package outline and PCB design information VFBGA36
© NXP B.V. 2021. All rights reserved.
High performance multi-protocol NFC frontend CLRC663 and CLRC663 plus
© NXP B.V. 2021. All rights reserved.
© NXP B.V. 2021. All rights reserved.
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| CLRC663 | NXP Semiconductors | — |
| CLRC66301 | NXP Semiconductors | — |
| CLRC66303 | NXP Semiconductors | — |
| CLRC66303A0EV | NXP Semiconductors | — |
| CLRC66303HN | NXP Semiconductors | — |
| CLRC66303HNE | NXP Semiconductors | — |
| CLRC66303HNY | NXP Semiconductors | 32-VFQFN Exposed Pad |
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