CL21B473KBCNNNC

Part: CL Series Multilayer Ceramic Capacitors from Samsung Electro-mechanics

Type: Multilayer Ceramic Capacitors (MLCC)

Description: A comprehensive series of Multilayer Ceramic Capacitors (MLCCs) offering a wide selection of sizes from 01005 (0402) to 2220 (5750) inch (mm), various dielectric characteristics (Class I C0G and Class II X5R, X7R, X6S, Y5V, X7S, X7T), and rated voltages from 2.5Vdc to 3kVdc, designed for highly reliable performance and high-speed automatic chip placement.

Operating Conditions:

• Supply voltage: 2.5Vdc–3kVdc
• Operating temperature: -55 to +125 °C (depending on dielectric)
• Pulse (dv/dt) Guarantee: 10,000V/us max.

Absolute Maximum Ratings:

• Max supply voltage: 3kVdc
• Max continuous current: null
• Max junction/storage temperature: +125 °C (based on highest operating temperature)

Key Specs:

• Capacitance Range: From pF to μF (e.g., up to 220 μF for X5R)
• Rated Voltage Range: 2.5Vdc to 3kVdc
• Dielectric Types: C0G, X5R, X7R, X6S, Y5V, X7S, X7T
• Capacitance Tolerance: From ±0.03pF to -20, +80%
• Temperature Coefficient (C0G): 0±30 ppm/°C over -55 ~ +125 °C
• Capacitance Change (X5R, X7R): ±15% over -55 ~ +85 °C (X5R) or -55 ~ +125 °C (X7R)
• Size Range: 01005 (0402) to 2220 (5750) inch (mm)
• Termination Plating: Ni / Sn 100%

Features:

• Wide selection of size: from 0402(Inch) to 2220(Inch)
• Highly reliable tolerance and high speed automatic chip placement on PCBs
• Wide capacitance range
• Highly reliable performance
• Highly resistant termination metal
• Tape & reel for surface mount assembly

Applications:

• Mobile Phone
• DC - DC Converter
• Tablet devices
• PC (Laptop, Desktop)
• HDD / SSD board
• Display

Package:

• 01005(0402)
• 0201(0603)
• 0402(1005)
• 0603(1608)
• 0805(2012)
• 1206(3216)
• 1210(3225)
• 1808(4520)
• 1812(4532)
• 2220(5750)

When designing printed circuit boards, the shape and size of the solder lands must allow for the proper amount of solder on the capacitor. The amount of solder at the end terminations has a direct effect on the probability that the chip will crack. The greater amount of solder, the larger amount of stress on the chip, and the more likely that it will break. Use the following illustrations as guidelines for proper Solder land design.