ATTINY816592

Part: ATtiny416/816

Type: 8-bit AVR Microcontroller

Description: 8-bit AVR microcontroller running at up to 20 MHz with 4/8 KB Flash, 512B SRAM, 128B EEPROM, and Core Independent Peripherals in a 20-pin package.

Operating Conditions:

• Supply voltage: 1.8–5.5 V
• Operating temperature: -40 to 105 °C
• Maximum CPU clock frequency: 20 MHz (at 4.5–5.5 V)

Features:

• 8-bit AVR CPU with hardware multiplier running at up to 20 MHz
• Up to 8 KB in-system self-programmable Flash, 512B SRAM, and 128B EEPROM
• Core Independent Peripherals including Event System and Configurable Custom Logic (CCL)
• Internal clock options including 16/20 MHz internal RC and 32.768 kHz ultra-low-power RC oscillators
• One 16-bit Timer/Counter Type A, one 16-bit Timer/Counter Type B, and one 12-bit Timer/Counter Type D
• 10-bit 115 ksps Analog-to-Digital Converter (ADC) and 8-bit Digital-to-Analog Converter (DAC)
• USART with fractional baud rate generator, master/slave SPI, and TWI (I2C-compatible up to 1 MHz)
• Peripheral Touch Controller (PTC) supporting buttons, sliders, and wheels

Applications:

• Capacitive touch interfaces
• Low-power embedded control systems
• Sensor interface and processing

Package:

• 20-pin VQFN (3x3 mm)
• 20-pin SOIC300

• CPU
• -AVR ® CPU
• -Running at up to 20 MHz
• -Single-cycle I/O access
• -Two-level interrupt controller
• -Two-cycle hardware multiplier
• Memories
• -4/8 KB In-system self-programmable Flash memory
• -128B EEPROM
• -256/512B SRAM
• -Write/erase endurance:
• Flash: 10,000 cycles
• EEPROM: 100,000 cycles
• -Data retention: 40 years at 55°C
• System
• -Power-on Reset (POR)
• -Brown-out Detector (BOD)
• -Clock options:
• 16/20 MHz low-power internal RC oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
• 32.768 kHz external crystal oscillator

These bits select the Reset/UPDI pin configuration.

Note: When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively driving the output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.

The TWI module in AVR devices follows the electrical specifications and timing of I 2 C bus and SMBus. These specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus timeout period should be set in TWI master mode. Refer to 26.3.4.2 TWI Master Operation for more details.