ATTINY816592

Part: ATtiny416/816 Type: AVR Microcontroller

Key Specs:

• CPU Speed: Up to 20 MHz
• Flash Memory: 4/8 KB
• SRAM: 256/512 bytes
• EEPROM: 128 bytes
• I/O Lines: 18 programmable
• ADC Resolution: 10-bit
• ADC Sample Rate: 115

• CPU
  • AVR® CPU
  • Running at up to 20 MHz
  • Single-cycle I/O access
  • Two-level interrupt controller
  • Two-cycle hardware multiplier
• Memories
  • 4/8 KB In-system self-programmable Flash memory
  • 128B EEPROM
  • 256/512B SRAM
  • Write/erase endurance:
    • Flash: 10,000 cycles
    • EEPROM: 100,000 cycles
  • Data retention: 40 years at 55°C
• System
  • Power-on Reset (POR)
  • Brown-out Detector (BOD)
  • Clock options:
    • 16/20 MHz low-power internal RC oscillator
    • 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
    • 32.768 kHz external crystal oscillator
• External clock input
• Single-pin Unified Program and Debug Interface (UPDI)
• Three sleep modes:
  • Idle with all peripherals running for immediate wake-up
  • Standby
    • Configurable operation of selected peripherals
    • SleepWalking peripherals
  • Power-Down with full data retention
• Peripherals
  • One 16-bit Timer/Counter Type A (TCA) with a dedicated period register and three compare channels
  • One 16-bit Timer/Counter Type B (TCB) with input capture
  • One 12-bit Timer/Counter Type D (TCD) optimized for control applications
  • One 16-bit Real-Time Counter (RTC) running from external crystal or internal RC oscillator
  • Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator
  • One USART with fractional baud rate generator, auto-baud, and start-of-frame detection
  • One master/slave Serial Peripheral Interface (SPI)
  • One Two-Wire Interface (TWI) with dual address match
    • Philips I2C compatible
    • Standard mode (Sm, 100 kHz)
    • Fast mode (Fm, 400 kHz)
    • Fast mode plus (Fm+, 1 MHz)
  • One Analog Comparator (AC) with a low propagation delay
  • One 10-bit 115 ksps Analog-to-Digital Converter (ADC)
  • One 8-bit Digital-to-Analog Converter (DAC)
  • Multiple voltage references (VREF):
    • 0.55V
    • 1.1V
    • 1.5V
    • 2.5V
    • 4.3V
  • Event System (EVSYS) for CPU independent and predictable inter-peripheral signaling
  • Configurable Custom Logic (CCL) with two programmable look-up tables
  • Automated CRC memory scan (CRCSCAN)
  • Peripheral Touch Controller (PTC)(1)
    • Capacitive touch buttons, sliders, wheels and 2D surfaces
    • Wake-up on touch
    • Driven shield for improved moisture and noise handling performance
    • Up to six self capacitance channels
    • Up to nine mutual capacitance channels
  • External interrupt on all general purpose pins
• I/O and Packages:
  • 18 programmable I/O lines
• – 20-pin VQFN 3x3 mm
• 20-pin SOIC300
• Temperature Ranges:
  • -40°C to 105°C
  • -40°C to 125°C
• Speed Grades:
  • 0-5 MHz @ 1.8V 5.5V
  • 0-10 MHz @ 2.7V 5.5V
  • 0-20 MHz @ 4.5V 5.5V

Note:

1. Only available in devices with 8 KB Flash.

• Introduction1

• Features 1

• 1. Silicon Errata and Data Sheet Clarification Document 11
• 1. tinyAVR® 1-series Overview12
     2.1.
     Configuration Summary12
• 1. Block Diagram 14
• 1. Pinout 16
     4.1.
     20-pin SOIC16
     4.2.
     20-pin VQFN 17
• 1. I/O Multiplexing and Considerations18

• 5.1.
  Multiplexed Signals 18

• 6.
  7. Memories19
  6.1.
  Overview 19
  6.2.
  Memory Map 20
  6.3.
  In-System Reprogrammable Flash Program Memory20
  6.4.
  SRAM Data Memory 21
  6.5.
  EEPROM Data Memory 21
  6.6.
  User Row21
  6.7.
  Signature Bytes21
  6.8.
  I/O Memory22
  6.9.
  FUSES - Configuration and User Fuses 24
  Peripherals and Architecture 44
  7.1.
  Peripheral Module Address Map44
  7.2.
  Interrupt Vector Mapping45
  7.3.
  SYSCFG - System Configuration47

• 1. AVR CPU50
     8.1.
     Features 50
     8.2.
     Overview 50
     8.3.
     Architecture 50
     8.4.
     ALU - Arithmetic Logic Unit 52
     8.5.
     Functional Description53
     8.6.
     Register Summary - CPU58
     8.7.
     Register Description58
• 1. NVMCTRL - Non Volatile Memory Controller 62
     9.1.
     Features 62
     9.2.
     Overview 62

• 9.3. Functional Description63

• 9.4. Register Summary - NVMCTRL70

• 9.5. Register Description70

• 1. CLKCTRL - Clock Controller 78

• 10.1. Features 78

• 10.2. Overview 78

• 10.3. Functional Description80

• 10.4. Register Summary - CLKCTRL85

• 10.5. Register Description85

• 1. SLPCTRL - Sleep Controller 95

• 11.1. Features 95

• 11.2. Overview 95

• 11.3. Functional Description96

• 11.4. Register Summary - SLPCTRL 99

• 11.5. Register Description99

• 1. RSTCTRL - Reset Controller101

• 12.1. Features 101

• 12.2. Overview 101

• 12.3. Functional Description102

• 12.4. Register Summary - RSTCTRL105

• 12.5. Register Description105

• 1. CPUINT - CPU Interrupt Controller 108

• 13.1. Features 108

• 13.2. Overview 108

• 13.3. Functional Description110

• 13.4. Register Summary - CPUINT 116

• 13.5. Register Description 116

• 1. EVSYS - Event System 121

• 14.1. Features 121

• 14.2. Overview 121

• 14.3. Functional Description124

• 14.4. Register Summary - EVSYS 126

• 14.5. Register Description126

• 1. PORTMUX - Port Multiplexer 133

• 15.1. Overview 133

• 15.2. Register Summary - PORTMUX 134

• 15.3. Register Description134

• 1. PORT - I/O Pin Configuration 139

• 16.1. Features 139

• 16.2.
  16.3. Overview 139
  Functional Description141

• 16.5.
  Register Description - Ports 145

• 16.6.
  Register Summary - VPORT 157

• 16.7.
  Register Description - Virtual Ports 157

• 17.
  BOD - Brownout Detector162

• 17.1.
  Features 162
  17.2.
  Overview 162

• 17.3.
  Functional Description164

• 17.4.
  Register Summary - BOD166

• 17.5.
  Register Description166

• 18.
  VREF - Voltage Reference 173

• 18.1.
  Features 173

• 18.2.
  Overview 173

• 18.3.
  Functional Description173

• 18.4.
  Register Summary - VREF175

• 18.5.
  Register Description175

• 19.
  WDT - Watchdog Timer 178

• 19.1.
  Features 178

• 19.2.
  Overview 178

• 19.3.
  Functional Description180

• 19.4.
  Register Summary - WDT 184

• 19.5.
  Register Description184

• 20.
  TCA - 16-bit Timer/Counter Type A 188

• 20.1.
  Features 188

• 20.2.
  Overview 188

• 20.3.
  Functional Description192

• 20.4.
  Register Summary - TCA in Normal Mode (CTRLD.SPLITM=0) 202

• 20.5.
  Register Description - Normal Mode 202

• 20.6.
  Register Summary - TCA in Split Mode (CTRLD.SPLITM=1)222

• 20.7.
  Register Description - Split Mode222

• 21.
  TCB - 16-bit Timer/Counter Type B 238

• 21.1.
  Features 238

• 21.2.
  Overview 238

• 21.3.
  Functional Description241

• 21.4.
  Register Summary - TCB 249

• 21.5.
  Register Description249

• 22.
  TCD - 12-bit Timer/Counter Type D261

• 22.1.
  Features 261

• 22.2.
  Overview 261

• 22.3.
  Functional Description265

• 22.4.
  Register Summary - TCD287

• 22.5.
  Register Description287

• 23.
  RTC - Real Time Counter307

• 23.1.
  Features 307

• 23.2.
  Overview 307

• 23.3.
  RTC Functional Description 310

• 23.4.
  PIT Functional Description 310

• 23.5.
  Events311

• 23.6.
  Interrupts 311

• 23.7.
  Sleep Mode Operation 312

• 23.8.
  Synchronization312

• 23.9.
  Configuration Change Protection 312

• 23.10. Register Summary - RTC313

• 23.11. Register Description313

• 24.
  USART - Universal Synchronous and Asynchronous Receiver and Transmitter 329

• 24.1.
  Features 329

• 24.2.
  Overview 329

• 24.3.
  Functional Description332

• 24.4.
  Register Summary - USART 347

• 24.5.
  Register Description347

• 25.
  SPI - Serial Peripheral Interface366

• 25.1.
  Features 366

• 25.2.
  Overview 366

• 25.3.
  Functional Description369

• 25.4.
  Register Summary - SPI377

• 25.5.
  Register Description377

• 26.
  TWI - Two Wire Interface384

• 26.1.
  Features 384

• 26.2.
  Overview 384

• 26.3.
  Functional Description386

• 26.4.
  Register Summary - TWI400

• 26.5.
  Register Description400

• 27.
  CRCSCAN - Cyclic Redundancy Check Memory Scan 418

• 27.1.
  Features 418

• 27.2.
  Overview 418

• 27.3.
  Functional Description420

• 27.4.
  Register Summary - CRCSCAN423

• 27.5.
  Register Description423

• 28.
  CCL – Configurable Custom Logic427

• 28.1.
  Features 427

• 28.2.
  Overview 427

• 28.3.
  Functional Description429

• 28.4.
  Register Summary - CCL 438

• 28.5.
  Register Description438

• 1. AC – Analog Comparator 445

• 29.1. Features 445

• 29.2. Overview 445

• 29.3. Functional Description447

• 29.4. Register Summary - AC 449

• 29.5. Register Description449

• 1. ADC - Analog to Digital Converter454

• 30.1. Features 454

• 30.2. Overview 454

• 30.3. Functional Description458

• 30.4. Register Summary - ADC467

• 30.5. Register Description467

• 1. DAC - Digital to Analog Converter485

• 31.1. Features 485

• 31.2. Overview 485

• 31.3. Functional Description487

• 31.4. Register Summary - DAC489

• 31.5. Register Description489

• 1. PTC - Peripheral Touch Controller492

• 32.1. Features 492

• 32.2. Overview 492

• 32.3. Functional Description495

• 1. UPDI - Unified Program and Debug Interface 497

• 33.1. Features 497

• 33.2. Overview 497

• 33.3. Functional Description500

• 33.4. Register Summary - UPDI520

• 33.5. Register Description520

• 1. Electrical Characteristics 531

• 34.1. Disclaimer531

• 34.2. Absolute Maximum Ratings 531

• 34.3. General Operating Ratings 532

• 34.4. Power Consumption for ATtiny416533

• 34.5. Power Consumption for ATtiny816534

• 34.6. Wake-Up Time536

• 34.7. Peripherals Power Consumption536

• 34.8. BOD and POR Characteristics537

• 34.9. External Reset Characteristics538

• 34.10. Oscillators and Clocks538

• 34.11. I/O Pin Characteristics540

• 34.12. USART542

• 34.15. Bandgap and VREF 546

• 34.16. ADC547

• 34.17. DAC549

• 34.18. AC 550

• 34.19. PTC551

• 34.20. UPDI Timing552

• 34.21. Programming Time552

• 35.
  Typical Characteristics554

• 35.1.
  Power Consumption554

• 35.2.
  GPIO 569

• 35.3.
  VREF Characteristics577

• 35.4.
  BOD Characteristics579

• 35.5.
  ADC Characteristics582

• 35.6.
  AC Characteristics587

• 35.7.
  OSC20M Characteristics589

• 35.8.
  OSCULP32K Characteristics 591

• 35.9.
  TWI SDA Hold timing for ATtiny816 592

• 35.10. PTC Characteristics for ATtiny816592

• 36.
  Ordering Information595

• 36.1.
  Product Information595

• 36.2.
  Product Identification System595

• 37.
  Packaging Information597

• 37.1.
  Package Drawings 597

• 37.2.
  Thermal Considerations 605

• 38.
  Instruction Set Summary 606

• 39.
  Conventions612

• 39.1.
  Numerical Notation612

• 39.2.
  Memory Size and Type612

• 39.3.
  Frequency and Time612

• 39.4.
  Registers and Bits 613

• 40.
  Acronyms and Abbreviations614

• 41.
  Errata617

• 41.1.
  Errata - ATtiny416/816 617

• 42.
  Datasheet Revision History 618

• 42.1.
  Rev. B - 07/2019618

• 42.2.
  Rev. A - 01/2017619

• The Microchip Website620

• Customer Support 620

• Microchip Devices Code Protection Feature 620
• Legal Notice621
• Trademarks 621
• Quality Management System 622
• Worldwide Sales and Service623

These bits select the Reset/UPDI pin configuration.

Note: When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively driving the output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.

The TWI module in AVR devices follows the electrical specifications and timing of I2C bus and SMBus. These specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus timeout period should be set in TWI master mode. Refer to 26.3.4.2 TWI Master Operation for more details.