ATTINY816592

Part: ATtiny416/816

Type: tinyAVR 1-series Microcontroller

Description: AVR processor with hardware multiplier, running at up to 20 MHz, with 4/8 KB Flash, 256/512 bytes of SRAM, and 128 bytes of EEPROM in a 20-pin package, featuring Event System, SleepWalking, and Core Independent Peripherals.

Operating Conditions:

• Supply voltage: 1.8V–5.5V
• Operating temperature: -40°C to 125°C
• Max CPU frequency: 20 MHz

Key Specs:

• CPU Speed: up to 20 MHz
• Flash Memory: 4/8 KB In-system self-programmable
• SRAM: 256/512 bytes
• EEPROM: 128 bytes
• Flash endurance: 10,000 cycles
• EEPROM endurance: 100,000 cycles
• ADC: 10-bit, 115 ksps
• DAC: 8-bit
• I/O lines: 18 programmable

Features:

• AVR CPU with single-cycle I/O access and two-cycle hardware multiplier
• Two-level interrupt controller
• Power-on Reset (POR) and Brown-out Detector (BOD)
• Internal RC oscillators (16/20 MHz, 32.768 kHz ULP) and external crystal support
• Single-pin Unified Program and Debug Interface (UPDI)
• Three sleep modes: Idle, Standby, Power-Down
• Multiple Timer/Counters: One 16-bit TCA, one 16-bit TCB, one 12-bit TCD, one 16-bit RTC
• Watchdog Timer (WDT) with Window mode
• Communication interfaces: One USART, one master/slave SPI, one TWI (I2C compatible: Sm, Fm, Fm+)
• Analog Comparator (AC)
• Multiple voltage references (0.55V, 1.1V, 1.5V, 2.5V, 4.3V)
• Event System (EVSYS)
• Configurable Custom Logic (CCL)
• Automated CRC memory scan (CRCSCAN)
• Peripheral Touch Controller (PTC) for capacitive touch with driven shield
• External interrupt on all general purpose pins

Package:

• 20-pin VQFN 3x3 mm
• 20-pin SOIC300

• CPU
• -AVR ® CPU
• -Running at up to 20 MHz
• -Single-cycle I/O access
• -Two-level interrupt controller
• -Two-cycle hardware multiplier
• Memories
• -4/8 KB In-system self-programmable Flash memory
• -128B EEPROM
• -256/512B SRAM
• -Write/erase endurance:
• Flash: 10,000 cycles
• EEPROM: 100,000 cycles
• -Data retention: 40 years at 55°C
• System
• -Power-on Reset (POR)
• -Brown-out Detector (BOD)
• -Clock options:
• 16/20 MHz low-power internal RC oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
• 32.768 kHz external crystal oscillator

These bits select the Reset/UPDI pin configuration.

Note: When configuring the Reset Pin as GPIO, there is a potential conflict between the GPIO actively driving the output, and a 12V UPDI enable sequence initiation. To avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a System Reset. Enable any interrupts for this pin only after this period.

The TWI module in AVR devices follows the electrical specifications and timing of I 2 C bus and SMBus. These specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus timeout period should be set in TWI master mode. Refer to 26.3.4.2 TWI Master Operation for more details.