ATSAMD21G18A-AU

Part: ATSAMD21G18A

Type: 32-bit ARM Cortex-M0+ MCU

Description: Low-power 32-bit ARM Cortex-M0+ MCU running at up to 48 MHz with up to 256 KB Flash, up to 32 KB SRAM, and extensive peripheral integration including USB, 12-bit ADC, and 10-bit DAC.

Operating Conditions:

• Supply voltage: 1.62V - 3.63V
• Operating temperature: -40 to +125 °C
• Max CPU frequency: 48 MHz

Key Specs:

• CPU: ARM Cortex-M0+
• Flash Memory: 32/64/128/256 KB in-system self-programmable
• SRAM Memory: 4/8/16/32 KB
• ADC: 12-bit, 350ksps, up to 20 channels
• DAC: 10-bit, 350 ksps
• SERCOM: Up to six, configurable as USART, I2C (up to 3.4 MHz), SPI, LIN slave
• USB: Full-speed (12 Mbps) 2.0 interface with embedded host and device function
• I/O Pins: Up to 52 programmable

Features:

• Single-cycle hardware multiplier
• Micro Trace Buffer (MTB)
• Low-power Idle and Stand-by Sleep modes with SleepWalking peripherals
• 12-channel Direct Memory Access Controller (DMAC)
• Peripheral Touch Controller (PTC) with 256-Channel capacitive touch
• 32-bit Real Time Counter (RTC) with clock/calendar function

Package:

• 64-pin TQFP, QFN, UFBGA
• 48-pin TQFP, QFN
• 45-pin WLCSP
• 35-pin WLCSP
• 32-pin TQFP, QFN

• Processor

• -ARM ® Cortex ® -M0+ CPU running at up to 48 MHz

• Single-cycle hardware multiplier

• Micro Trace Buffer (MTB)

• Memories

• -32/64/128/256 KB in-system self-programmable Flash

• -4/8/16/32 KB SRAM Memory

• System

• -Power-on Reset (POR) and Brown-out Detection (BOD)

• -Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M) and 48 MHz to 96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)

• -External Interrupt Controller (EIC)

• -16 external interrupts

• -One Non-maskable Interrupt (NMI)

• -Two-pin Serial Wire Debug (SWD) programming, test and debugging interface

• Low Power

• -Idle and Stand-by Sleep modes

• -SleepWalking peripherals

• Peripherals

• -12-channel Direct Memory Access Controller (DMAC)

• -12-channel Event System

• -Up to five 16-bit Timer/Counters (TC), configurable as either:

• One 16-bit TC with two compare/capture channels

• One 8-bit TC with two compare/capture channels

• One 32-bit TC with two compare/capture channels, by using two TCs

• -Up to four 24-bit Timer/Counters for Control (TCC), with extended functions:

• Up to four compare channels with optional complementary output

• Generation of synchronized pulse width modulation (PWM) pattern across port pins

• Deterministic fault protection, fast decay and configurable dead-time between complementary output

• Dithering that increase resolution with up to 5 bit and reduce quantization error

• -32-bit Real Time Counter (RTC) with clock/calendar function

• -Watchdog Timer (WDT)

• -CRC-32 generator

• -One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface

• Embedded host and device function

• Eight endpoints

• -Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:

• USART with full-duplex and single-wire half-duplex configuration

• I 2 C up to 3.4 MHz

• SPI

• LIN slave

• -One two-channel Inter-IC Sound (I 2 S) interface

• -One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels

• Differential and single-ended input

• 1/2x to 16x programmable gain stage

• Automatic offset and gain error compensation

• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution

• -10-bit, 350 ksps Digital-to-Analog Converter (DAC)

• -Up to four Analog Comparators (AC) with Window Compare function

• -Peripheral Touch Controller (PTC)

• 256-Channel capacitive touch and proximity sensing

• I/O

• -Up to 52 programmable I/O pins

• Qualification

• -AEC-Q100 Grade 1 (-40°C to 125°C)

• Drop-in compatible with SAM D20

• Packages

• -64-pin TQFP, QFN, UFBGA

• -48-pin TQFP, QFN

• -45-pin WLCSP

• -35-pin WLCSP

• -32-pin TQFP, QFN

• Operating Voltage

• -1.62V - 3.63V

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole or pull configuration.

As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided.

The I/O pin configurations are described further in this chapter, and summarized in Table 23-2.