ATSAMD21G18

The ATSAMD21G18 is an electronic component from Microchip Technology. View the full ATSAMD21G18 datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

Microchip Technology

Overview

Part: ATSAMD21J18A-AU

Type: Low-Power, 32-bit Cortex-M0+ MCU

Description: 32-bit ARM Cortex-M0+ MCU running at up to 48 MHz with up to 256 KB Flash, 32 KB SRAM, advanced analog peripherals including 12-bit ADC and 10-bit DAC, and a full-speed USB 2.0 interface.

Operating Conditions:

Supply voltage: 1.62V - 3.63V
Operating temperature: -40°C to 125°C
Max CPU frequency: 48 MHz

Key Specs:

CPU: ARM Cortex-M0+
Max CPU Frequency: 48 MHz
Flash Memory: up to 256 KB
SRAM Memory: up to 32 KB
ADC: 12-bit, 350 ksps, up to 20 channels
DAC: 10-bit, 350 ksps
USB: Full-speed (12 Mbps) 2.0 interface
I/O Pins: Up to 52 programmable I/O pins

Features:

Single-cycle hardware multiplier
Micro Trace Buffer (MTB)
Power-on Reset (POR) and Brown-out Detection (BOD)
Idle and Stand-by Sleep modes
Up to six Serial Communication Interfaces (SERCOM) configurable as USART, I2C, SPI, LIN slave
Peripheral Touch Controller (PTC) with 256-Channel capacitive touch

Package:

64-pin TQFP, QFN, UFBGA
48-pin TQFP, QFN
45-pin WLCSP
35-pin WLCSP
32-pin TQFP, QFN

Features

Processor
-ARM ® Cortex ® -M0+ CPU running at up to 48 MHz
Single-cycle hardware multiplier
Micro Trace Buffer (MTB)
Memories
-32/64/128/256 KB in-system self-programmable Flash
-4/8/16/32 KB SRAM Memory
System
-Power-on Reset (POR) and Brown-out Detection (BOD)
-Internal and external clock options with 48 MHz Digital Frequency-Locked Loop (DFLL48M) and 48 MHz to 96 MHz Fractional Digital Phase-Locked Loop (FDPLL96M)
-External Interrupt Controller (EIC)
-16 external interrupts
-One Non-maskable Interrupt (NMI)
-Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
-Idle and Stand-by Sleep modes
-SleepWalking peripherals
Peripherals
-12-channel Direct Memory Access Controller (DMAC)
-12-channel Event System
-Up to five 16-bit Timer/Counters (TC), configurable as either:
One 16-bit TC with two compare/capture channels
One 8-bit TC with two compare/capture channels
One 32-bit TC with two compare/capture channels, by using two TCs
-Up to four 24-bit Timer/Counters for Control (TCC), with extended functions:
Up to four compare channels with optional complementary output
Generation of synchronized pulse width modulation (PWM) pattern across port pins
Deterministic fault protection, fast decay and configurable dead-time between complementary output
Dithering that increase resolution with up to 5 bit and reduce quantization error
-32-bit Real Time Counter (RTC) with clock/calendar function
-Watchdog Timer (WDT)
-CRC-32 generator
-One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
Embedded host and device function
Eight endpoints
-Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
USART with full-duplex and single-wire half-duplex configuration
I 2 C up to 3.4 MHz
SPI
LIN slave
-One two-channel Inter-IC Sound (I 2 S) interface
-One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
Differential and single-ended input
1/2x to 16x programmable gain stage
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
-10-bit, 350 ksps Digital-to-Analog Converter (DAC)
-Up to four Analog Comparators (AC) with Window Compare function
-Peripheral Touch Controller (PTC)
256-Channel capacitive touch and proximity sensing
I/O
-Up to 52 programmable I/O pins
Qualification
-AEC-Q100 Grade 1 (-40°C to 125°C)
Drop-in compatible with SAM D20
Packages
-64-pin TQFP, QFN, UFBGA
-48-pin TQFP, QFN
-45-pin WLCSP
-35-pin WLCSP
-32-pin TQFP, QFN
Operating Voltage
-1.62V - 3.63V

Applications

Updated description in 31.6.1 Principle of Operation.

Updated description in sub sections of 31.6.2 Basic Operation.

Updated description in sub sections of 31.6.3 Additional Features.

Updated description in 31.6.6 Synchronization.

Lock Update (LUPD) bit description updated in Control B Clear (CTRLBCLR) register.

Compare Channel Buffer x Busy (CCBx) bit description updated in Synchronization Busy (SYNCBUSY) register.

Event Control (EVCTRL) register property updated: Removed Enable-Protected.

Interrupt Enable Clear (INTENCLR), Interrupt Enable Set (INTENSET) and Interrupt Flag Status and Clear (INTFLAG) registers: Updated bit description of FAULT0, FAULT1, FAULTA and FAULTB.

STATUS register bit descriptions updated.

Wave Control (WAVE) register property updated: Removed Read-Synchronized.

Pattern Buffer (PATTB) register: Updated property and bit description.

Waveform Control Buffer (WAVEB) register: Updated property and bit descriptions.

Pin Configuration

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totem-pole or pull configuration.

As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided.

The I/O pin configurations are described further in this chapter, and summarized in Table 23-2.

Electrical Characteristics

...........continued		Max.	Units
f GCLK_EVSYS_CHANNEL_8	EVSYS channel 8 input clock frequency	48	MHz
f GCLK_EVSYS_CHANNEL_9	EVSYS channel 9 input clock frequency	48	MHz
f GCLK_EVSYS_CHANNEL_10	EVSYS channel 10 input clock frequency	48	MHz
f GCLK_EVSYS_CHANNEL_11	EVSYS channel 11 input clock frequency	48	MHz
f GCLK_SERCOMx_SLOW	Common SERCOM slow input clock frequency	48	MHz
f GCLK_SERCOM0_CORE	SERCOM0 input clock frequency	48	MHz
f GCLK_SERCOM1_CORE	SERCOM1 input clock frequency	48	MHz
f GCLK_SERCOM2_CORE	SERCOM2 input clock frequency	48	MHz
f GCLK_SERCOM3_CORE	SERCOM3 input clock frequency	48	MHz
f GCLK_SERCOM4_CORE	SERCOM4 input clock frequency	48	MHz
f GCLK_SERCOM5_CORE	SERCOM5 input clock frequency	48	MHz
f GCLK_TCC0 , f GCLK_TCC1	TCC0, TCC1 input clock frequency	96	MHz
f GCLK_TCC2 , f GCLK_TCC3 , f GCLK_TC3	TCC2, TCC3, TC3 input clock frequency	96	MHz
f GCLK_TC4 , f GCLK_TC5	TC4, TC5 input clock frequency	48	MHz
f GCLK_TC6 , f GCLK_TC7	TC6, TC7 input clock frequency	48	MHz
f GCLK_ADC	ADC input clock frequency	48	MHz
f GCLK_AC_DIG	AC digital input clock frequency	48	MHz
f GCLK_AC_ANA	AC analog input clock frequency	64	KHz
f GCLK_AC1_DIG	AC1 digital input clock frequency	48	MHz
f GCLK_AC1_ANA	AC1 analog input clock frequency	64	KHz
f GCLK_DAC	DAC input clock frequency	350	KHz
f GCLK_PTC	PTC input clock frequency	48	MHz
f GCLK_I2S_0	I2S serial 0 input clock frequency	13	MHz
f GCLK_I2S_1	I2S serial 1 input clock frequency	13	MHz

Absolute Maximum Ratings

Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 37-2. Absolute Maximum Ratings

Symbol	Description	Min.	Max.	Units
V DD	Power supply voltage	0	3.8	V
I VDD	Current into a V DD pin	-	92 (1)	mA
I GND	Current out of a GND pin	-	130 (1)	mA
V PIN	Pin voltage with respect to GND and V DD	GND-0.6V	V DD +0.6V	V
T storage	Storage temperature	-60	150	°C

Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of GPIOs as shown in the table below. Also note that each VDD/GND pair is connected to two clusters so current consumption through the pair will be a sum of the clusters source/sink currents.

CAUTION

This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to permanent performance degradation or malfunctioning.

Handle the device following best practice ESD protection rules: Be aware that the human body can accumulate charges large enough to impair functionality or destroy the device.

CAUTION

In debugger cold-plugging mode, NVM erase operations are not protected by the BOD33 and BOD12. NVM erase operation at supply voltages below specified minimum can cause corruption of NVM areas that are mandatory for correct device behavior.

7.2.4 GPIO Clusters

Thermal Information

The following Table summarizes the thermal resistance data depending on the package.

Table 37-1. Thermal Resistance Data

Package Type	θ JA	θ JC
32-pin TQFP	64.7°C/W	23.1°C/W
48-pin TQFP	63.6°C/W	12.2°C/W
64-pin TQFP	60.9°C/W	12.2°C/W
32-pin QFN	40.9°C/W	15.2°C/W
48-pin QFN	32.0°C/W	10.9°C/W
64-pin QFN	32.5°C/W	10.7°C/W
35-ball WLCSP	41.8°C/W	2.26°C/W
45-ball WLCSP	43.97°C/W	2.91°C/W
64-pin UFBGA	53°C/W	4.74°C/W

Package Information

Note: For current package drawings, refer to the Microchip Packaging Specification, which is available at http://www.microchip.com/packaging.

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
ATSAMD21	Microchip Technology	—
ATSAMD21E18A-AU	Microchip Technology	32-TQFP
ATSAMD21J18A	Microchip Technology	—
ATSAMD21J18A-AU	Microchip Technology	64-TQFP

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