AP63203WU

Part: AP63200/AP63201/AP63203/AP63205 from Diodes Incorporated

Type: Synchronous Buck Converter

Key Specs:

• Input Voltage Range: 3.8V to 32V
• Continuous Output Current: 2A
• Reference Voltage: 0.8V ±1%
• Ultralow Quiescent Current: 22µA
• Switching Frequency: 500kHz (AP63200, AP63201)
• Switching Frequency: 1.1MHz (AP63203, AP63205)
• High-side Power MOSFET: 125mΩ
• Low-side Power MOSFET: 68mΩ
• Light Load Efficiency (1mA): Up to 80%
• Light Load Efficiency (5mA): Up to 88%

Features:

• VIN 3.8V to 32V
• 2A Continuous Output Current
• 0.8V ±1% Reference Voltage
• 22µA Ultralow Quiescent Current
• Switching Frequency
• Pulse Width Modulation (PWM) Regardless of Output Load (AP63201)
• Supports Pulse Frequency Modulation (PFM) (AP63200, AP63203, and AP63205)
• Up to 80% Efficiency at 1mA Light Load
• Up to 88% Efficiency at 5mA Light Load
• Fixed Output Voltage (3.3V: AP63203, 5.0V: AP63205)
• Proprietary Gate Driver Design for Best EMI Reduction
• Frequency Spread Spectrum (FSS) to Reduce EMI
• Precision Enable Threshold to Adjust UVLO
• Overvoltage Protection
• Cycle-by-Cycle Peak Current Limit
• Thermal Shutdown
• Totally Lead-Free & Fully RoHS Compliant
• Halogen and Antimony Free. "Green" Device

Applications:

• 12V and 24V distributed power bus supplies
• Flat screen TV sets and monitors
• Power tools and laser printers
• White goods and small home appliances
• FPGA, DSP, and ASIC supplies
• Home audios
• Network systems
• Set top boxes
• Gaming consoles
• Consumer electronics

Package:

• TSOT26: dimensions not specified

• VIN 3.8V to 32V
• 2A Continuous Output Current
• 0.8V ±1% Reference Voltage
• 22µA Ultralow Quiescent Current
• Switching Frequency
  • o 500kHz: AP63200 and AP63201
  • o 1.1MHz: AP63203 and AP63205
• Pulse Width Modulation (PWM) Regardless of Output Load
  • o AP63201
• Supports Pulse Frequency Modulation (PFM)
  • o AP63200, AP63203, and AP63205
  • o Up to 80% Efficiency at 1mA Light Load
  • o Up to 88% Efficiency at 5mA Light Load
• Fixed Output Voltage
  • o 3.3V: AP63203
  • o 5.0V: AP63205
• Proprietary Gate Driver Design for Best EMI Reduction
• Frequency Spread Spectrum (FSS) to Reduce EMI
• Precision Enable Threshold to Adjust UVLO
• Protection Circuitry
  • o Overvoltage Protection
  • o Cycle-by-Cycle Peak Current Limit
  • o Thermal Shutdown
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
• Halogen and Antimony Free. "Green" Device (Note 3)
• An automotive-compliant part is available under separate datasheet (AP63200Q/AP63201Q/AP63203Q/AP63205Q)

• 12V and 24V distributed power bus supplies

• Flat screen TV sets and monitors

• Power tools and laser printers

• White goods and small home appliances

• FPGA, DSP, and ASIC supplies

• Home audios

• Network systems

• Set top boxes

• Gaming consoles

• Consumer electronics

• Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant.

  • 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated's definitions of Halogen- and Antimony-free, "Green" and Lead-free.
  • 1. Halogen- and Antimony-free "Green" products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.

Typical Application Circuit

Figure 1. Typical Application Circuit

Figure 2. Efficiency vs. Output Current

Pin Descriptions

Functional Block Diagram

Figure 3. Functional Block Diagram

Absolute Maximum Ratings (Note 4) (@T^A = +25°C, unless otherwise specified.)

Thermal Resistance (Note 6)

| Symbol | Parameter | Rating | Unit | |--------|---------------------|--------|------|------| | θJA | Junction to Ambient | TSOT26 | 89 | °C/W | | θJC | Junction to Case | TSOT26 | 39 | °C/W |

Note: 6. Test condition for TSOT26: Device mounted on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout.

Recommended Operating Conditions (Note 7) (@T^A = +25°C, unless otherwise specified.)

Note: 7. The device function is not guaranteed outside of the recommended operating conditions.

Notes: 4. Stresses greater than those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to "Absolute Maximum Ratings" for extended periods can affect device reliability.

^5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices.

Electrical Characteristics (T^A = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended ambient temperature range, -40°C to +85°C, and input voltage range, 3.8V to 32V.)

Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.

Typical Performance Characteristics (AP63200 @T^A = +25°C, VIN = 12V, VOUT = 5V, unless otherwise specified.)

Figure 6. Load Regulation, VOUT = 5V Figure 7. Line Regulation, VOUT = 5V

Figure 8. Feedback Voltage vs. Temperature Figure 9. Power Switch RDS(ON) vs. Temperature

Typical Performance Characteristics (continued)

Figure 10. IQ vs. Temperature Figure 11. ISHDN vs. Temperature

Figure 12. FSW vs. Temperature Figure 13. VIN POR and UVLO vs. Temperature

Figure 14. Startup using EN, Iout = 2A Figure 15. Shutdown using EN, Iout = 2A

Application Information

Figure 20. Typical Application Circuit of AP63200/AP63201

Figure 21. Typical Application Circuit of AP63203/AP63205

1 PWM Operation Control

The AP63200/AP63201/AP63203/AP63205 device is a 3.8V-to-32V input, 2A output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram in Figure 3. The device employs fixed-frequency peak current mode control. The internal clock's rising edge (500kHz for the AP6300 and AP63201, 1.1MHz for the AP63203 and AP63205) initiates turning on the integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on, the inductor current rises linearly, and the device charges the output capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of $R_T$ via the CSA block. The CSA output is combined with an internal slope compensation, $S_E$ , resulting in $V_{SUM}$ . When $V_{SUM}$ rises higher than the internal COMP node, the device turns off Q1 and turns on the low-side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off, and Q1 turns on. This sequence repeats every clock cycle.

The peak current mode control with the internal loop compensation network and built-in 4ms soft-start simplifies the AP63200/AP63201/AP63203/AP63205 footprint as well as minimizes the external component count.

The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the increased load current. This feedback loop regulates the output voltage. The device also integrates internal slope compensation circuitry to prevent subharmonic oscillation when the duty cycle is greater than 50% for peak current mode control.

The AP63200/AP63201/AP63203/AP63205 device implements Frequency Spread Spectrum (FSS) with a switching frequency jitter of ±6%. FSS reduces EMI by not allowing emitted energy to stay in any one frequency for a significant period of time. The converter further dampens high frequency radiated EMI noise through the use of its proprietary gate driver scheme to achieve a ringing-free switching node voltage without sacrificing the MOSFET switching times.

In order to provide a small output ripple in light load conditions, the AP63201 offers a fixed 500kHz switching frequency with FSS and Pulse Width Modulation (PWM).

The hiccup mode minimizes power dissipation during prolonged output overcurrent or short conditions. The hiccup wait time is 512 cycles and the hiccup restart time is 8192 cycles. The AP63200/AP63201/AP63203/AP63205 also features full protections including cycle-by-cycle high-side MOSFET peak current limit, overvoltage protection, and overtemperature protection.

2 Pulse Frequency Modulation

In heavy load conditions, the AP63200, AP63203, and AP63205 operate at forced PWM mode. The internal COMP node voltage decreases as the load current decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further. The voltage at which COMP is clamped corresponds to the 450mA peak inductor current. As the load current approaches zero, the AP63200, AP63203, and AP63205 enter Pulse Frequency Modulation (PFM) to increase the converter power efficiency at light load conditions. The AP63201 remains in continuous conduction mode at light load conditions. When the inductor current decreases to zero, zero-cross detection circuitry on the low-side power MOSFET, Q2, forces it off until the beginning of the next switching cycle. The buck converter does not sink current from the output when the output load is light and while the device is in PFM. Because the AP63200, AP63203, and AP63205 work in PFM during light load conditions, they can achieve power efficiency of up to 88% at a 5mA load condition.

The quiescent current of the AP63200, AP63203 and AP63205 is 22μA typical under a no-load, non-switching condition.

3 Enable

When disabled, the device shutdown supply current is only 1μA. When applying a voltage higher than the EN upper threshold (typical 1.18V, rising), the AP63200/AP63201/AP63203/AP63205 enables all functions, and the device initiates the soft-start phase. The AP63200/AP63201/AP63203/AP63205 has a built-in 4ms soft-start time to prevent output voltage overshoot and inrush current. When the EN voltage falls below its lower threshold (typical 1.1V, falling), the internal SS voltage is discharged to ground and device operation is disabled.

An internal 1.5µA pull-up current source connected from the internal LDO-regulated VCC to the EN pin guarantees that a high on the EN pin automatically enables the device. For applications requiring a higher VIN UVLO voltage than is provided by the default setup, there is a 4µA hysteresis pull-up current source on the EN pin that configures the VIN UVLO voltage with an external resistive divider (R5 and R6) shown in Figure 22. The resistive divider resistor values are calculated by equations Eq.1 and Eq.2.

Figure 22. Programming UVLO

$$R_{5} = \frac{0.932 \cdot V_{ON} - V_{OFF}}{4.1 \mu A} \label{eq:R5}$$ Eq. 1

$$R_6 = \frac{1.,1R_5}{V_{0FF} - 1.,1V + 5.,5\mu\text{A}\cdot\text{R}_5} \label{eq:R6}$$ Eq. 2

Where:

• VON is the rising edge voltage to enable the regulator
• VOFF is the falling edge voltage to disable the regulator

Alternatively, a small ceramic capacitor can be added from EN to GND. This delays the output startup voltage, which is useful when sequencing multiple power rails to minimize input inrush current. The amount of capacitance is calculated by equation Eq.3.

$$C_d[\mathrm{nF}] = 1.27 \cdot t_S[ms]$$ Eq. 3

Where:

• Cd is the time delay capacitance in nF
• ts is the delay time in ms

The EN pin is a high voltage pin and can be directly connected to VIN to automatically start up the device as VIN increases.

4 Undervoltage Lockout

Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP63200/AP63201/AP63203/AP63205 device has a UVLO comparator that monitors the input voltage and the internal bandgap reference. If the input voltage falls below 3.1V, the AP63200/AP63201/AP63203/AP63205 is disabled. In this event, both the high-side and low-side power MOSFETs are turned off.

5 EMI Reduction with Frequency Spread Spectrum and Ringing-free Switching Node

In some applications, the system must meet EMI standards. To improve EMI reduction, the AP63200/AP63201/AP63203/AP63205 adopts FSS to spread the switching noise over a wider frequency band and therefore reduces conducted and radiated interference at a particular frequency.

In buck converters, the switching node's (SW's) ringing amplitude and cycles are critical, especially in relation to the high frequency radiation EMI noise. The AP63200/AP63201/AP63203/AP63205 device implements a multi-level gate driver scheme to achieve a ringing-free switching node without sacrificing neither the switching node's rise and fall slew rates nor the converter's power efficiency. The AP63203 and AP63205 also have the feature to remove the resonance ringing of the SW pin when the inductor current is 0A and the device operates in PFM. The zoomed in waveform for SW is shown in Figure 23.

Figure 23. AP63203/AP63205 SW Node Waveform

6 Overcurrent Protection

The AP63200/AP63201/AP63203/AP63205 has cycle-by-cycle peak current limit protection by sensing the current through the internal high-side power MOSFET Q1. While Q1 is on, its conduction current is monitored by the internal sensing circuitry. Once the current through Q1 exceeds the current peak limit, Q1 immediately turns off. If Q1 consistently hits the peak current limit for 2ms, the buck converter enters hiccup mode and shuts down. After 16ms of off time, the buck converter restarts powering up. Hiccup mode reduces the power dissipation in the overcurrent condition.

7 Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of +150°C, the AP63200/AP63201/AP63203/AP63205 shuts down both their high-side and low-side power MOSFETs. When the junction temperature reduces to the required level (+130°C nominal), the device initiates a normal power-up cycle with soft-start.

8 Power Derating Characteristics

To prevent the regulator from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by:

$$T_{RISE} = PD \cdot (\theta_{JA})$$ Eq. 4

Where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature.

The junction temperature, TJ, is given by:

$$\mathbf{T}{!J} = \mathbf{T}{!A} + \mathbf{T}_{!RISE}$$ Eq. 5

Where TA is the ambient temperature of the environment. For the TSOT26 package, the JA is 89°C/W. The actual junction temperature should not exceed the absolute maximum junction temperature of +125°C when considering the thermal design. A typical derating curve versus ambient temperature is shown in Figure 24.

Figure 24. Output Current Derating Curve vs. Temperature, VIN = 12V

9 Setting the Output Voltage

The AP63203 and AP63205 have fixed output voltages of 3.3V and 5V, respectively. The AP63200 and AP63201 have adjustable output voltages starting from 0.8V using an external resistive divider. An optional in Figure 20, of 10pF to 220pF is used to improve the transient response. Resistor R2 is selected based on a design tradeoff between efficiency and output voltage accuracy. There is less current consumption in the feedback network for high values of R2. R1 can be determined by the following equation:

$$\mathbf{R_1} = \mathbf{R_2} \cdot (\frac{\mathbf{V_{OUT}}}{0.8\mathbf{V}} - \mathbf{1})$$ Eq. 6

Table 1 shows a list of recommended component selections for common output voltages for the AP63200 and AP63201 referencing Figure 20.

| | AP63200/AP63201 | |--------------------|-----------------|---------|--------|---------|---------|---------|---------| | Output Voltage (V) | R1 (k) | R2 (k) | L (µH) | C1 (µF) | C2 (µF) | C3 (nF) | C4 (pF) | | 1.2 | 30.9 | 62 | 2.2 | 10 | 2 x 22 | 100 | 100 | | 1.5 | 54.2 | 62 | 2.2 | 10 | 2 x 22 | 100 | 100 | | 1.8 | 77.5 | 62 | 3.3 | 10 | 2 x 22 | 100 | 100 | | 2.5 | 131 | 62 | 3.3 | 10 | 2 x 22 | 100 | 100 | | 3.3 | 196 | 62 | 6.8 | 10 | 2 x 22 | 100 | 100 | | 5 | 157 | 30 | 10 | 10 | 2 x 22 | 100 | 100 | | 12 | 249 | 18 | 10 | 10 | 2 x 22 | 100 | 56 |

Table 1. Recommended Component Selections for AP63200/AP63201

Tables 2 and 3 show recommended component selections for the AP63203 and AP63205 referencing Figure 21.

| AP63203 | |--------------------|--------|---------|---------|---------| | Output Voltage (V) | L (µH) | C1 (µF) | C2 (µF) | C3 (nF) | | 3.3 | 3.9 | 10 | 2 x 22 | 100 |

Table 2. Recommended Component Selections for AP63203

| AP63205 | |--------------------|--------|---------|---------|---------|--| | Output Voltage (V) | L (µH) | C1 (µF) | C2 (µF) | C3 (nF) | | 5 | 4.7 | 10 | 2 x 22 | 100 | Table 3. Recommended Component Selections for AP63205

10 Inductor

Calculating the inductor value is a critical factor in designing a buck converter. For most designs, the following equation can be used to calculate the inductor value:

$$\mathbf{L} = \frac{\mathbf{V}{OUT} \cdot (\mathbf{V}{IN} - \mathbf{V}{OUT})}{\mathbf{V}{IN} \cdot \Delta \mathbf{I}L \cdot \mathbf{f}{sw}}$$ Eq. 7

Where ∆IL is the inductor ripple current, and fSW is the buck converter switching frequency. For AP63200/AP63201/AP63203/AP63205, choose ∆IL to be 30% to 50% of the maximum load current of 2A.

The inductor peak current is calculated by:

$$I_{L_{PEAK}} = I_{LOAD} + \frac{\Delta I_L}{2}$$ Eq. 8

Peak current determines the required saturation current rating, which influences the size of the inductor. Saturating the inductor decreases the converter efficiency while increasing the temperatures of the inductor and the internal power MOSFETs. Therefore, choosing an inductor with the appropriate saturation current rating is important. For most applications, it is recommended to select an inductor of approximately 2.2µH to 10µH with a DC current rating of at least 35% higher than the maximum load current. For highest efficiency, the inductor's DC resistance should be less than 100mΩ. Use a larger inductance for improved efficiency under light load conditions.

11 Input Capacitor

The input capacitor reduces the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor has to sustain the ripple current produced during the on time of Q1. It must have a low ESR to minimize the losses.

The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rule of thumb, select an input capacitor which has an RMS rating greater than half of the maximum load current.

Due to large dI/dt through the input capacitor, electrolytic, or ceramics with low ESR should be used. If a tantalum capacitor is used it must be surge protected or else capacitor failure could occur. Using a ceramic capacitor greater than 10µF is sufficient for most applications.

12 Output Capacitor

The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces the overshoot/undershoot of the output voltage during load transients. During the first few milliseconds of a load transient, the output capacitor supplies the current to the load. The converter recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value.

The output capacitor, COUT, requirements can be calculated from equations Eq. 9 and Eq. 10.

The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated from Eq. 9:

$$V_{OUT_{Ripple}} = \Delta I_L \cdot ESR$$ Eq. 9

An output capacitor with large capacitance and low ESR is the best option. For most applications, a 22µF to 68µF ceramic capacitor is sufficient. To meet the load transient requirement, COUT should be greater than the following calculated from Eq. 10:

$$C_{OUT}>\frac{L\cdot\left(I_{OUT}+\frac{\Delta I_L}{2}\right)^2}{(\Delta V+V_{OUT})^2-V_{OUT}^2}$$ Eq. 10

Where ΔV is the maximum output overshoot voltage.

13 Bootstrap Capacitor

To ensure the proper operation, a ceramic capacitor must be connected between the BST and SW pins. A 100nF ceramic capacitor is sufficient. If the BST capacitor voltage falls below 2.3V, the boot undervoltage protection circuit turns Q2 on for 220ns to refresh the BST capacitor and raise its voltage back above 2.85V. The BST capacitor voltage threshold is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with light load conditions. Another event requires the refreshing of the BST capacitor is when the input voltage drops close to the output voltage. Under this condition, the regulator enters low dropout mode by holding Q1 on for multiple clock cycles. To prevent the BST capacitor from discharging, Q2 is forced to refresh. The effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage regulation.

Layout

PCB Layout

• 1. The AP63200/AP63201/AP63203/AP63205 device works at 2A current load, so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and bottom layers is recommended.
• 1. Provide sufficient vias for the input and output capacitors' GND side to dissipate heat to the bottom layer.
• 1. Make the bottom layer under the device as the GND layer for heat dissipation. The GND layer should be as large as possible to provide better thermal effect.
• 1. Place the VIN capacitors as close to the device as possible.
• 1. Place the feedback components as close to FB as possible.
• 1. See Figure 25 for reference.

Figure 25. Recommended Layout

Ordering Information

Please see http://www.diodes.com/package-outlines.html for additional latest information such as Mechanical Data and Device Tape Orientation.

| Orderable Part Number | Deelsone | e Mode Frequency V _OUT | | V | Dockers Code | Packing | |-----------------------|----------|-----------------------------------|---------|------------|--------------|---------|----------------| | Orderable Part Number | Package | | | VOUT | Package Code | Qty. | Carrier | | AP63200WU-7 | TSOT26 | PWM/PFM | 500kHz | Adjustable | WU | 3000 | 7" Tape & Reel | | AP63201WU-7 | TSOT26 | PWM Only | 500kHz | Adjustable | WU | 3000 | 7" Tape & Reel | | AP63203WU-7 | TSOT26 | PWM/PFM | 1100kHz | 3.3V | WU | 3000 | 7" Tape & Reel | | AP63205WU-7 | TSOT26 | PWM/PFM | 1100kHz | 5V | WU | 3000 | 7" Tape & Reel |

Note: 7. The device function is not guaranteed outside of the recommended operating conditions.

Notes: 4. Stresses greater than those listed under "Absolute Maximum Ratings" can cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to "Absolute Maximum Ratings" for extended periods can affect device reliability.

^5. Semiconductor devices are ESD sensitive and can be damaged by exposure to ESD events. Suitable ESD precautions should be taken when handling and transporting these devices.

Electrical Characteristics (T^A = +25°C, VIN = 12V, unless otherwise specified. Min/Max limits apply across the recommended ambient temperature range, -40°C to +85°C, and input voltage range, 3.8V to 32V.)

Note: 8. Compliance to the datasheet limits is assured by one or more methods: production test, characterization, and/or design.

| Symbol | Parameter | Rating | Unit | |--------|---------------------|--------|------|------| | θJA | Junction to Ambient | TSOT26 | 89 | °C/W | | θJC | Junction to Case | TSOT26 | 39 | °C/W |

Note: 6. Test condition for TSOT26: Device mounted on FR-4 substrate, single-layer PC board, 2oz copper, with minimum recommended pad layout.