ADS1220

Table 2. ENOB from RMS Noise (Noise-Free Bits from Peak-to-Peak Noise) at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, and Internal Reference = 2.048 V

Manufacturer

Overview

Part: ADS1220

Type: 24-Bit Analog-to-Digital Converter (ADC)

Key Specs:

Low Current Consumption: As low as 120 μA (typ) in Duty-Cycle Mode
Wide Supply Range: 2.3 V to 5.5 V
Programmable Gain: 1 V/V to 128 V/V
Programmable Data Rates: Up

Features

Low Current Consumption: As Low as 120 μA (typ) in Duty-Cycle Mode

Wide Supply Range: 2.3 V to 5.5 V

Programmable Gain: 1 V/V to 128 V/V

Programmable Data Rates: Up to 2 kSPS

Up to 20-Bits Effective Resolution

Simultaneous 50-Hz and 60-Hz Rejection at 20 SPS with Single-Cycle Settling Digital Filter

Two Differential or Four Single-Ended Inputs

Dual Matched Programmable Current Sources: 10 μ A to 1.5 mA

Internal 2.048-V Reference: 5 ppm/°C (typ) Drift

Internal 2% Accurate Oscillator

Internal Temperature Sensor: 0.5°C (typ) Accuracy

SPI-Compatible Interface (Mode 1)

Package: 3.5-mm × 3.5-mm × 0.9-mm VQFN

Applications

Temperature Sensor Measurements:
- Thermistors
- Thermocouples
- Resistance Temperature Detectors (RTDs): 2-, 3-, or 4-Wire Types
Resistive Bridge Sensor Measurements:
- Pressure Sensors
- Strain Gauges
- Weigh Scales
Portable Instrumentation
Factory Automation and Process Control

Pin Configuration

Pin Functions

	PIN
	N
NAME	RVA
AIN0/REFP1	9
AIN1	8
AIN2	5
AIN3/REFN1	4
AVDD	10
AVSS	3
CLK	1
CS	16
DGND	2
DIN	14
DOUT/DRDY	13
DRDY	12
DVDD	11
REFN0	6
REFP0	7
SCLK	15
Thermal pad

(1) See the Unused Inputs and Outputs section for unused pin connections.

Electrical Characteristics

Minimum and maximum specifications apply from T^A = –40°C to +125°C. Typical specifications are at T^A = 25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external Vref = 2.5 V (unless otherwise noted).(1)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
	ANALOG INPUTS
	Absolute input current			See the Typical Characteristics
	Differential input current			See the Typical Characteristics
	SYSTEM PERFORMANCE
	Resolution (no missing codes)		24			Bits
		Normal mode		20, 45, 90, 175, 330, 600, 1000
DR	Data rate	Duty-cycle mode		5, 11.25, 22.5, 44, 82.5, 150, 250		SPS
		Turbo mode		40, 90, 180, 350, 660, 1200, 2000
	Noise (input-referred)			See the Noise Performance section
INL	Integral nonlinearity	Gain = 1 to 128, VCM = 0.5 AVDD, best fit(2)	–15	±6	15	ppmFSR
		PGA disabled, gain = 1 to 4, differential inputs		±4
VIO	Input offset voltage	Gain = 1, differential inputs, TA = 25°C	–30	±4	30	μV
		Gain = 2 to 128, differential inputs		±4
		PGA disabled, gain = 1 to 4		0.25
	Offset drift	(2) Gain = 1 to 128, TA = –40°C to +85°C		0.08	0.3	μV/°C
		Gain = 1 to 128		0.25
	Offset match	Match between any two inputs		±20		μV
		PGA disabled, gain = 1 to 4		±0.015%
	Gain error	Gain = 1 to 128, TA = 25°C	–0.1%	±0.015%	0.1%
		PGA disabled, gain = 1 to 4		1
	Gain drift	Gain = 1 to 128(2)		1	4	ppm/°C
		50 Hz ±3%, DR = 20 SPS, external CLK, 50/60 bit = 10	105
NMRR	Normal-mode rejection ratio(2)	60 Hz ±3%, DR = 20 SPS, external CLK, 50/60 bit = 11	105			dB
		50 Hz or 60 Hz ±3%, DR = 20 SPS, external CLK, 50/60 bit = 01	90
		At dc, gain = 1	90	105
CMRR	Common-mode rejection ratio	(2) f(CM) = 50 Hz, DR = 2000 SPS	95	115		dB
		f(CM) = 60 Hz, DR = 2000 SPS(2)	95	115
		AVDD at dc, VCM = 0.5 AVDD, gain = 1	80	105
PSRR	Power-supply rejection ratio	(2) DVDD at dc, VCM = 0.5 AVDD, gain = 1	100	115		dB
	INTERNAL VOLTAGE REFERENCE
	Initial accuracy	TA = 25°C	2.045	2.048	2.051	V
	Reference drift(2)			5	30	ppm/°C
	Long-term drift	1000 hours		110		ppm
	VOLTAGE REFERENCE INPUTS
	Reference input current	REFP0 = Vref, REFN0 = AVSS		±10		nA
	INTERNAL OSCILLATOR
	Internal oscillator accuracy	Normal mode	–2%	±1%	2%
⁽¹⁾ PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case. See the Bypassing the PGA section for more information.

⁽²⁾ Minimum and maximum values are ensured by design and characterization data.

Absolute Maximum Ratings

		MIN	MAX	UNIT
	AVDD to AVSS	–0.3	7	V
Power-supply voltage	DVDD to DGND	–0.3	7	V
	AVSS to DGND	–2.8	0.3	V
Analog input voltage	AIN0/REFP1, AIN1, AIN2, AIN3/REFN1, REFP0, REFN0	AVSS – 0.3	AVDD + 0.3	V
Digital input voltage	CS, SCLK, DIN, DOUT/DRDY, DRDY, CLK	DGND – 0.3	DVDD + 0.3	V
Input current	Continuous, any pin except power supply pins	–10	10	mA
	Junction, TJ	–40	150	°C
Temperature	Storage, Tstg	–60	150	°C

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)	±2000
V(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101(2)	±500	V

⁽¹⁾ JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

⁽²⁾ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
POWER SUPPLY
		AVDD to AVSS	2.3		5.5
	Unipolar analog power supply	AVSS to DGND	–0.1	0	0.1	V
		AVDD to DGND	2.3	2.5	2.75
	Bipolar analog power supply	AVSS to DGND	–2.75	–2.5	–2.3	V
	Digital power supply	DVDD to DGND	2.3		5.5	V
	ANALOG INPUTS(1)
VIN	Differential input voltage	(2) VIN = V(AINP) – V(AINN)	–Vref / Gain		Vref / Gain	V
		PGA disabled, gain = 1 to 4	AVSS – 0.1		AVDD + 0.1	V
V(AINx)	Absolute input voltage	PGA enabled, gain = 1 to 128		See the Low-Noise PGA section
		PGA disabled, gain = 1 to 4	AVSS – 0.1		AVDD + 0.1	V
VCM	Common-mode input voltage	PGA enabled, gain = 1 to 128		See the Low-Noise PGA section
	VOLTAGE REFERENCE INPUTS(3)
Vref	Differential reference input voltage	Vref = V(REFPx) – V(REFNx)	0.75	2.5	AVDD	V
V(REFNx)	Absolute negative reference voltage		AVSS – 0.1		V(REFPx) – 0.75	V
V(REFPx)	Absolute positive reference voltage		V(REFNx) + 0.75		AVDD + 0.1	V
	EXTERNAL CLOCK SOURCE
f(CLK)	External clock frequency		0.5	4.096	4.5	MHz
	Duty cycle		40%		60%
DIGITAL INPUTS
	Input voltage		DGND		DVDD	V
	TEMPERATURE RANGE
TA	Operating ambient temperature		–40		125	°C

⁽¹⁾ AIN^P and AIN^N denote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs. PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case. See the Bypassing the PGA section for more information.

6.4 Thermal Information

			ADS1220
	THERMAL METRIC(1)	VQFN (RVA)	TSSOP (PW)
		16 PINS	16 PINS
RθJA	Junction-to-ambient thermal resistance	43.4	99.5
RθJC(top)	Junction-to-case (top) thermal resistance	47.3	35.2
RθJB	Junction-to-board thermal resistance	18.4	44.3
ψJT	Junction-to-top characterization parameter	0.6	2.4
ψJB	Junction-to-board characterization parameter	18.4	43.8
RθJC(bot)	Junction-to-case (bottom) thermal resistance	2.0	n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

⁽²⁾ Excluding the effects of offset and gain error. Limited to ±[(AVDD – AVSS) – 0.4 V] / Gain, when the PGA is enabled.

⁽³⁾ REFPx and REFNx denote one of two available differential reference input pairs.

Thermal Information

			ADS1220
	THERMAL METRIC(1)	VQFN (RVA)	TSSOP (PW)
		16 PINS	16 PINS
RθJA	Junction-to-ambient thermal resistance	43.4	99.5
RθJC(top)	Junction-to-case (top) thermal resistance	47.3	35.2
RθJB	Junction-to-board thermal resistance	18.4	44.3
ψJT	Junction-to-top characterization parameter	0.6	2.4
ψJB	Junction-to-board characterization parameter	18.4	43.8
RθJC(bot)	Junction-to-case (bottom) thermal resistance	2.0	n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

⁽²⁾ Excluding the effects of offset and gain error. Limited to ±[(AVDD – AVSS) – 0.4 V] / Gain, when the PGA is enabled.

⁽³⁾ REFPx and REFNx denote one of two available differential reference input pairs.

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