ADS1120IPWR

Part: ADS1120, Texas Instruments

Type: 4-Channel, 2-kSPS, Low-Power, 16-Bit ADC with Integrated PGA and Reference

Key Specs:

• Low Current Consumption: 120 μA (typ) in Duty-Cycle Mode
• Wide Supply Range: 2.3 V to 5.5 V
• Programmable Gain: 1 V/V to 12

Low Current Consumption: As Low as 120 μA (typ) in Duty-Cycle Mode

Wide Supply Range: 2.3 V to 5.5 V

Programmable Gain: 1 V/V to 128 V/V

Programmable Data Rates: Up to 2 kSPS

16-Bit Noise-Free Resolution at 20 SPS

Simultaneous 50-Hz and 60-Hz Rejection at 20 SPS with Single-Cycle Settling Digital Filter

Two Differential or Four Single-Ended Inputs

Dual-Matched Programmable Current Sources: 50 μA to 1.5 mA

Internal 2.048-V Reference: 5 ppm/°C (typ) Drift

Internal 2% Accurate Oscillator

Internal Temperature Sensor: 0.5°C (typ) Accuracy

SPI-Compatible Interface (Mode 1)

Package: 3.5-mm × 3.5-mm × 0.9-mm VQFN

• Temperature Sensor Measurements:
  • Thermistors
  • Thermocouples
  • Resistance Temperature Detectors (RTDs): 2-, 3-, or 4-Wire Types
• Resistive Bridge Sensor Measurements:
  • Pressure Sensors
  • Strain Gauges
  • Weigh Scales
• Portable Instrumentation
• Factory Automation and Process Controls

Pin Functions

(1) See the Unused Inputs and Outputs section for unused pin connections.

6 Specifications

6.1 Absolute Maximum Ratings(1)

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

⁽¹⁾ JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process..

⁽²⁾ JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

⁽¹⁾ AIN^P and AIN^N denote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs. PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case. See the Bypassing the PGA section for more information.

6.4 Thermal Information

⁽²⁾ Excluding the effects of offset and gain error. Limited to ±[(AVDD – AVSS) – 0.4 V] / Gain, when the PGA is enabled.

⁽³⁾ REFPx and REFNx denote one of two available differential reference input pairs.

6.5 Electrical Characteristics

Minimum and maximum specifications apply from T^A = –40°C to +125°C. Typical specifications are at T^A = 25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external Vref = 2.5 V (unless otherwise noted).(1)

⁽²⁾ Minimum and maximum values are ensured by design and characterization data.

Electrical Characteristics (continued)

Minimum and maximum specifications apply from T^A = –40°C to +125°C. Typical specifications are at T^A = 25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external Vref = 2.5 V (unless otherwise noted).(1)

6.6 SPI Timing Requirements

over operating ambient temperature range and DVDD = 2.3 V to 5.5 V (unless otherwise noted)

⁽¹⁾ CS can be tied low permanently in case the serial bus is not shared with any other device.

6.7 SPI Switching Characteristics

over operating ambient temperature range, DVDD = 2.3 V to 5.5 V (unless otherwise noted)

NOTE: Single-byte communication is shown. Actual communication may be multiple bytes.

Figure 1. Serial Interface Timing Requirements

NOTE: Single-byte communication is shown. Actual communication may be multiple bytes.

Figure 2. Serial Interface Switching Characteristics

⁽²⁾ See the SPI Timeout section for more information. t(MOD) = 1 / f(MOD). Modulator frequency f(MOD) = 256 kHz (normal mode, duty-cycle mode) and 512 kHz (turbo mode), when using the internal oscillator or an external 4.096-MHz clock.

6.8 Typical Characteristics

At T^A = 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external Vref = 2.5 V (unless otherwise noted).

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At T^A = 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external Vref = 2.5 V (unless otherwise noted).

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At T^A = 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external Vref = 2.5 V (unless otherwise noted).

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At T^A = 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external Vref = 2.5 V (unless otherwise noted).

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Differential Input Voltage

Differential Input Voltage

At T^A = 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external Vref = 2.5 V (unless otherwise noted).

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At T^A = 25°C, AVDD = 3.3 V, AVSS = 0 V, and PGA enabled using external Vref = 2.5 V (unless otherwise noted).

7 Parameter Measurement Information

7.1 Noise Performance

Delta-sigma (ΔSigma) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔSigma ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 1 to Table 8 summarize the device noise performance. Data are representative of typical noise performance at T_A = 25^°C using the internal 2.048-V reference. Data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. Table 1, Table 3, Table 5 and Table 7 list the input-referred noise in units of μ V_RMS for the conditions shown. Note that μ V_PP values are shown in parenthesis. Table 2, Table 4, Table 6 and Table 8 list the corresponding data in effective number of bits (ENOB) calculated from μ V_RMS values using Equation 1. Note that noise-free bits calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

The input-referred noise (Table 1, Table 3, Table 5 and Table 7) only changes marginally when using an external low-noise reference, such as the REF5020. To calculate ENOB numbers and noise-free bits when using a reference voltage other than 2.048 V, use Equation 1 to Equation 3:

$$ENOB = In (Full-Scale Range / VRMS-Noise) / In(2)$$ (1)

Noise-Free Bits = $ln (Full-Scale Range / V_PP-Noise) / ln(2)$ (2)

Full-Scale Range = $2 · V_ref / Gain$ (3)

Table 1. Noise in $\mu V_{RMS}$ ( $\mu V_{PP}) at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, and Internal Reference = 2.048 V

Table 2. ENOB from RMS Noise (Noise-free Bits from Peak-to-Peak Noise) at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, and Internal Reference = 2.048 V

Table 3. Noise in μVRMS (μVPP) with PGA Disabled at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, and Internal Reference = 2.048 V

Table 5. Noise in μVRMS (μVPP) at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, and Internal Reference = 2.048 V

Table 6. ENOB from RMS Noise (Noise-Free Bits from Peak-to-Peak Noise) at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, and Internal Reference = 2.048 V

Table 7. Noise in μVRMS (μVPP) with PGA Disabled at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, and Internal Reference = 2.048 V

8 Detailed Description

8.1 Overview

The ADS1120 is a small, low-power, 16-bit,\Delta\Sigma$ ADC that offers many integrated features to reduce system cost and component count in applications measuring small sensor signals.

In addition to the $\Delta\Sigma$ ADC core and single-cycle settling digital filter, the device offers a low-noise, high input impedance, programmable gain amplifier (PGA), an internal voltage reference, and a clock oscillator. The device also integrates a highly linear and accurate temperature sensor as well as two matched programmable current sources (IDACs) for sensor excitation. All of these features are intended to reduce the required external circuitry in typical sensor applications and improve overall system performance. An additional low-side power switch eases the design of low-power bridge sensor applications. The device is fully configured through four registers and controlled by six commands through a mode 1 SPI-compatible interface. The Functional Block Diagram section shows the device functional block diagram.

The ADS1120 ADC measures a differential signal, $V_{IN}$ , which is the difference in voltage between nodes $AIN_P$ and $AIN_N$ . The converter core consists of a differential, switched-capacitor, $\Delta\Sigmamodulator followed by a digital filter. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. This architecture results in a very strong attenuation of any common-mode signal.

The device has two available conversion modes: single-shot and continuous conversion mode. In single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value in an internal data buffer. The device then enters a low-power state to save power. Single-shot mode is intended to provide significant power savings in systems that require only periodic conversions, or when there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. New data are available at the programmed data rate. Data can be read at any time without concern of data corruption and always reflect the most recently completed conversion.

8.2 Functional Block Diagram


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8.3 Feature Description

8.3.1 Multiplexer

The device contains a very flexible input multiplexer, as shown in Figure 38. Either four single-ended signals, two differential signals, or a combination of two single-ended signals and one differential signal can be measured. The multiplexer is configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are measured, the negative ADC input (AINN) is internally connected to AVSS by a switch within the multiplexer. For system-monitoring purposes, the analog supply (AVDD – AVSS) / 4 or the currently-selected external reference voltage (V(REFPx) – V(REFNx)) / 4 can be selected as inputs to the ADC. The multiplexer also offers the possibility to route any of the two programmable current sources to any analog input (AINx) or to any dedicated reference pin (REFP0, REFN0).


Figure 38. Analog Input Multiplexer

Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range provided by Equation 4:AVSS - 0.3 V < V_(AINX) < AVDD + 0.3 V$

$tag{4}If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an unused input on the device may affect conversions taking place on other input pins. If any overdrive on unused inputs is possible, TI recommends clamping the signal with external Schottky diodes.


Feature Description (continued)

8.3.2 Low-Noise PGA

The device features a low-noise, low-drift, high input impedance, programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Three bits (GAIN[2:0]) in the configuration register are used to configure the gain. A simplified diagram of the PGA is shown in Figure 39. The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the PGA gain. The PGA input is equipped with an electromagnetic interference (EMI) filter.


Figure 39. Simplified PGA Diagram

V_{IN}$ denotes the differential input voltage $V_{IN} = (V_{(AINP)} - V_{(AINN)})$ . The gain of the PGA can be calculated with Equation 5:

$Gain = 1 + 2 · R_F / R_G tag{5}$

Gain is changed inside the device using a variable resistor, R_G. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 6:

$FSR = ± V_ref / Gain(6)

Table 9 shows the corresponding full-scale ranges when using the internal 2.048-V reference.

Table 9. PGA Full-Scale Range


8.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 39 can not swing closer to the supplies (AVSS and AVDD) than 200 mV. If the outputs OUT^P and OUT^N are driven to within 200 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition the output voltages must meet Equation 7:AVSS + 0.2 V ≤ V_(OUTN), V_(OUTP) ≤ AVDD - 0.2 V$

$$(7)$Translating the requirements of Equation 7 into requirements referred to the PGA inputs (AIN^P and AINN) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design, therefore the common-mode voltage at the output of the PGA can be assumed to be the same as the commonmode voltage of the input signal, as shown in Figure 40.


Figure 40. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 8:V_CM = frac{1}{2} ≤ft( V_(AINP) + V_(AINN) right) = frac{1}{2} ≤ft( V_(OUTP) + V_(OUTN) right)$ (8)

The voltages at the PGA inputs (AIN^P and AINN) can be expressed as Equation 9 and Equation 10:

$V_(AINP) = V_CM + frac{1}{2} V_IN$ (9)

$V_(AINN) = V_CM - frac{1}{2} V_IN$ (10)

The output voltages (V(OUTP) and V(OUTN)) can then be calculated as Equation 11 and Equation 12:

$V_(OUTP) = V_CM + frac{1}{2} Gain · V_IN$ (11)

$V_(OUTN) = V_CM - frac{1}{2} Gain · V_IN$ (12)

The requirements for the output voltages of amplifiers A1 and A2 (Equation 7) can now be translated into requirements for the input common-mode voltage range using Equation 11 and Equation 12, which are given in Equation 13 and Equation 14:

$V_{CM (MIN)} ≥ AVSS + 0.2 V + frac{1}{2} Gain · V_{IN (MAX)}$ (13)

$V_{CM (MAX)} ≤ AVDD - 0.2 V - frac{1}{2} Gain · V_{IN (MAX)}$ (14)

In order to calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (VIN (MAX)) that occurs in the application must be used. VIN (MAX) can be less than the maximum possible FS value.

In addition to Equation 13, the minimum VCM must also meet Equation 15 because of the specific design implementation of the PGA.

$V_{CM (MIN)} ≥ AVSS + frac{1}{4} (AVDD - AVSS)(15)


Figure 41 and Figure 42 show a graphical representation of the common-mode voltage limits for AVDD = 3.3 V and AVSS = 0 V, with gain = 1 and gain = 16, respectively.


The following discussion explains how to apply Equation 13 through Equation 15 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference,V_{ref} = 2.5 \text{ V}$ . The maximum possible differential input voltage $V_{IN} = (V_{(AINP)} - V_{(AINN)})$ that can be applied is then limited to the full-scale range of FSR = $\pm 2.5 \text{ V}$ / $16 = \pm 0.156 \text{ V}$ . Consequently, Equation 13 through Equation 15 yield an allowed $V_{CM}$ range of $1.45 \text{ V} \le V_{CM} \le 1.85 \text{ V}$ .

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to $V_{IN~(MAX)} = \pm 0.1V$ , for example, then this reduced input signal amplitude relaxes the $V_{CM}$ restriction to 1.0 $V \le V_{CM} \le 2.3V$ .

In the case of a fully-differential sensor signal, each input (AIN_P, AIN_N) can swing up to $\pm 50$ mV around the common-mode voltage ( $V_{(AINP)} + V_{(AINN)}$ ) / 2, which must remain between the limits of 1.0 V and 2.3 V. The output of a symmetrical wheatstone bridge is an example of a fully-differential signal. Figure 43 shows a situation where the common-mode voltage of the input signal is at the lowest limit. $V_{(OUTN)}$ is exactly at 0.2 V in this case. Any further decrease in common-mode voltage ( $V_{CM}$ ) or increase in differential input voltage ( $V_{IN}$ ) drives $V_{(OUTN)}below 0.2 V and saturates amplifier A2.


Figure 43. Example where V_CM is at Lowest Limit


In contrast, the signal of an RTD is of a pseudo-differential nature (if implemented as shown in the RTD Measurement section), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage between 0.95 V and 2.25 V. The positive input can then swing up toV_{IN~(MAX)} = 100$ mV above the negative input. Note that in this case the common-mode voltage changes at the same time the voltage on the positive input changes. That is, while the input signal swings between 0 V $\leq$ V ${IN} \leq$ V ${IN~(MAX)}$ , the common-mode voltage swings between $V_{(AINN)} \leq V_{CM} \leq V_{(AINN)} + \frac{1}{2} V_{IN~(MAX)}$ . Satisfying the common-mode voltage requirements for the maximum input voltage $V_{IN~(MAX)}ensures the requirements are met throughout the entire signal range.

Figure 44 and Figure 45 show examples of both fully-differential and pseudo-differential signals, respectively.


NOTE

Remember, common-mode voltage requirements with PGA enabled (Equation 13 to Equation 15) are as follows:

• V_{CM (MIN)} ≥ AVSS + ¼ (AVDD AVSS) -V_{CM (MIN)} \ge AVSS + 0.2 V + \frac{1}{2} Gain \cdot V_{IN (MAX)}$
• $V_{CM (MAX)} \leq AVDD 0.2 V \frac{1}{2} Gain \cdot V_{IN (MAX)}### 8.3.2.2 Bypassing the PGA

At gains of 1, 2, and 4, the device can be configured to disable and bypass the low-noise PGA by setting the PGA_BYPASS bit in the configuration register. Disabling the PGA lowers the overall power consumption and also removes the restrictions of Equation 13 through Equation 15 for the common-mode input voltage range,V_{CM}$ . The usable absolute and common-mode input voltage range is (AVSS - 0.1 V $\leq$ V_(AINX), V_CM $\leq$ AVDD + 0.1 V) when the PGA is disabled.

In order to measure single-ended signals that are referenced to AVSS ( $AIN_P = V_{IN}$ , $AIN_N = AVSS$ ), the PGA must be bypassed. Configure the device for single-ended measurements by either connecting one of the analog inputs to AVSS externally or by using the internal AVSS connection of the multiplexer (MUX[3:0] settings 1000 through 1011). When configuring the internal multiplexer for settings where $AIN_N = AVSS(MUX[3:0] = 1000 through 1011) the PGA is automatically bypassed and disabled irrespective of the PGA_BYPASS setting and gain is limited to 1, 2, and 4. In case gain is set to greater than 4, the device limits gain to 4.

When the PGA is disabled, the device uses a buffered switched-capacitor stage to obtain gains of 1, 2, and 4. An internal buffer in front of the switched-capacitor stage ensures that the effect on the input loading resulting from the capacitor charging and discharging is minimal. See Figure 21 to Figure 26 for the typical values of absolute input currents (current flowing into or out of each input) and differential input currents (difference in absolute current between positive and negative input) when the PGA is disabled.

For signal sources with high output impedance, external buffering may still be necessary. Note that active buffers introduce noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.

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8.3.3 Modulator

A\Delta\Sigma$ modulator is used in the ADS1120 to convert the analog input voltage into a pulse code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of $f_{(MOD)} = f_{(CLK)}$ / 16 in normal and duty-cycle mode and $f_{(MOD)} = f_{(CLK)}$ / 8 in turbo mode, where $f_{(CLK)}is either provided by the internal oscillator or the external clock source. Table 10 shows the modulator frequency for each operating mode using either the internal oscillator or an external clock of 4.096 MHz.

Table 10. Modulator Clock Frequency for Different Operating Modes⁽¹⁾

(1) Using the internal oscillator or an external 4.096-MHz clock.

8.3.4 Digital Filter

The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the different data rates and always settles within a single cycle. At data rates of 5 SPS and 20 SPS, the filter can be configured to reject 50-Hz or 60-Hz line frequencies or to simultaneously reject 50 Hz and 60 Hz. Two bits (50/60[1:0]) in the configuration register are used to configure the filter accordingly. The frequency responses of the digital filter are shown in Figure 46 to Figure 59 for different output data rates using the internal oscillator or an external 4.096-MHz clock.

The filter notches and output data rate scale proportionally with the clock frequency. For example, a notch that appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. Note that the internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate or conversion time, respectively, and filter notches consequently vary by the same amount. Consider using an external precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.



Figure 47. Detailed View of Filter Response (DR = 20 SPS)






8.3.5 Output Data Rate

Table 11 shows the actual conversion times for each data rate setting. The values provided are in terms oft_{(CLK)}$ cycles using an external clock with a clock frequency of $f_{(CLK)} = 4.096$ MHz. The data rates scale proportionally in case an external clock with a frequency other than 4.096 MHz is used.

Continuous conversion mode data rates are timed from one $\overline{DRDY}$ falling edge to the next $\overline{DRDY}$ falling edge. The first conversion starts 210 $\cdot$ t_(CLK) (normal mode, duty-cycle mode) or 114 $\cdot$ t_(CLK) (turbo mode) after the last SCLK falling edge of the START/SYNC command.

Single-shot mode data rates are timed from the last SCLK falling edge of the START/SYNC command to the $\overline{DRDY}$ falling edge and rounded to the next $t_{(CLK)}$ . In case the internal oscillator is used, an additional oscillator wake-up time of up to 50 $\mu$ s (normal mode, duty-cycle mode) or 25 $\mus (turbo mode) must be added in single-shot mode. The internal oscillator starts to power up at the first SCLK rising edge of the START/SYNC command. If an SCLK frequency higher than 160 kHz (normal mode, duty-cycle mode) or 320 kHz (turbo mode) is used, the oscillator may not be fully powered up at the end of the START/SYNC command. The ADC then waits until the internal oscillator is fully powered up before starting a conversion.

Single-shot conversion times in duty-cycle mode are the same as in normal mode. See the Duty-Cycle Mode section for more details on duty-cycle mode operation.

NOMINAL DATA RATE -3-dB BANDWIDTH ACTUAL CONVERSION TIME (t_(CLK)) CONTINUOUS CONVERSION MODE SINGLE-SHOT MODE Normal Mode 204768 204850 13.1 45 91120 91218 20.0 90 39.6 46128 46226 175 77.8 23664 23762 330 150.1 12464 12562 600 279.0 6896 6994 4144 4242 1000 483.8 Duty-Cycle Mode 5 13.1 823120 n/a 11.25 20.0 364560 n/a 22.5 39.6 184592 n/a 44 77.8 94736 n/a 82.5 150.1 49936 n/a 150 279.0 27664 n/a 250 483.8 16656 n/a Turbo Mode 26.2 102384 102434 90 39.9 45560 45618 180 23064 23122 79 2 350 155.6 11832 11890 660 300.3 6232 6290 3448 3506 1200 558.1 2000 967.6 2072 2130

Table 11. Conversion Times

Note that even though the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not affect the 50-Hz or 60-Hz rejection. To achieve the 50-Hz and 60-Hz rejection specified in the Electrical Characteristics, the external clock frequency must be 4.096 MHz. When using the internal oscillator, the conversion time and filter notches vary by the amount specified in the Electrical Characteristics table for oscillator accuracy.


8.3.6 Voltage Reference

The device offers an integrated low-drift, 2.048-V reference. For applications that require a different reference voltage value or a ratiometric measurement approach, the device offers two differential reference input pairs (REFP0, REFN0 and REFP1, REFN1). In addition, the analog supply (AVDD – AVSS) can be used as a reference.

The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal reference is selected. The internal voltage reference requires less than 25 μs to fully settle after power-up, when coming out of power-down mode, or when switching from an external reference source to the internal reference.

The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are dedicated reference inputs whereas REFP1 and REFN1 are shared with inputs AIN0 and AIN3, respectively. All reference inputs are internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required when using an external reference. When used in ratiometric applications, the reference inputs do not load the external circuitry. Note that the analog supply current increases when using an external reference because the reference buffers are enabled.

In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and drift of the voltage reference is reflected in the conversion result.

8.3.7 Clock Source

The device system clock can either be provided by the internal low-drift oscillator or by an external clock source on the CLK input. Connect the CLK pin to DGND before power-up or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator after two rising edges on the CLK pin are detected. The device then operates on the external clock. After the ADS1120 switches to the external clock, the device can only be switched back to the internal oscillator by cycling the power supplies or by sending a RESET command.

8.3.8 Excitation Current Sources

The device provides two matched programmable excitation current sources (IDACs) for RTD applications. The output current of the current sources can be programmed to 50 μA, 100 μA, 250 μA, 500 μA, 1000 μA, or 1500 μA using the respective bits (IDAC[2:0]) in the configuration register. Each current source can be connected to any of the analog inputs (AINx) as well as to any of the dedicated reference inputs (REFP0 and REFN0). Both current sources can also be connected to the same pin. Routing of the IDACs is configured by bits (I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care must be taken not to exceed the compliance voltage of the IDACs. In other words, limit the voltage on the pin where the IDAC is routed to ≤ (AVDD – 0.9 V), otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see the 3-Wire RTD Measurement section for more details).

The IDACs require up to 200 μs to start up after the IDAC current is programmed to the respective value using bits IDAC[2:0]. If configuration registers 2 and 3 are not written during the same WREG command, TI recommends to first set the IDAC current to the respective value using bits IDAC[2:0] and thereafter select the routing for each IDAC (I1MUX[2:0], I2MUX[2:0]).

In single-shot mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are set to a value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is issued.

Note that the analog supply current increases when enabling the IDACs (that is, when the IDAC[2:0] bits are set to a value other than 000). The IDAC circuit needs this bias current to operate even when the IDACs are not routed to any pin (I1MUX[2:0] = I2MUX[2:0] = 000). In addition, the selected output current is drawn from the analog supply when I1MUX[2:0] or I2MUX[2:0] are set to a value other than 000.


8.3.9 Low-Side Power Switch

A low-side power switch with low on-resistance connected between the analog input AIN3/REFN1 and AVSS is integrated in the device as well. This power switch can be used to reduce system power consumption in bridge sensor applications by powering down the bridge circuit between conversions. When the respective bit (PSW) in the configuration register is set, the switch automatically closes when the START/SYNC command is sent and opens when the POWERDOWN command is issued. Note that the switch stays closed between conversions in single-shot mode in case the PSW bit is set to 1. The switch can be opened at any time by setting the PSW bit to 0. By default, the switch is always open.

8.3.10 Sensor Detection

To help detect a possible sensor malfunction, the device provides internal 10-μA, burn-out current sources. When enabled by setting the respective bit (BCS) in the configuration register, one current source sources current to the positive analog input (AINP) currently selected while the other current source sinks current form the selected negative analog input (AINN).

In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading may also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading may indicate a shorted sensor. Note that the absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero.

Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are enabled. TI recommends disabling the burn-out current sources when preforming the precision measurement, and only enabling them to test for sensor fault conditions.

8.3.11 System Monitor

The device provides some means for monitoring the analog power supply and the external voltage reference. To select a monitoring voltage, the internal multiplexer (MUX[3:0]) must be configured accordingly in the configuration register. The device automatically bypasses the PGA and sets the gain to 1, irrespective of the configuration register settings while the monitoring feature is used. Note that the system monitor function only provides a coarse result and is not meant to be a precision measurement.

When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD – AVSS) / 4. The device uses the internal 2.048-V reference for the measurement regardless of what reference source is selected in the configuration register (VREF[1:0]).

When monitoring one of the two possible external reference voltage sources (MUX[3:0] = 1100), the result is approximately (V(REFPx) – V(REFNx)) / 4. REFPx and REFNx denote the external reference input pair selected in the configuration register (VREF[1:0]). The device automatically uses the internal reference for the measurement.

8.3.12 Offset Calibration

The internal multiplexer offers the option to short both PGA inputs (AIN^P and AINN) to mid-supply (AVDD + AVSS) / 2. This option can be used to measure and calibrate the device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and consequently subtracting the result from each following reading. TI recommends taking multiple readings with the inputs shorted and averaging the result to reduce the effect of noise.


8.3.13 Temperature Sensor

The ADS1120 offers an integrated precision temperature sensor. The temperature sensor mode is enabled by setting bit TS = 1 in the configuration register. When in temperature sensor mode, the settings of configuration register 0 have no effect and the device uses the internal reference for measurement, regardless of the selected voltage reference source. Temperature readings follow the same process as the analog inputs for starting and reading conversion results. Temperature data are represented as a 14-bit result that is left-justified within the 16 bit conversion result. Data are output starting with the most significant byte (MSB). When reading the two data bytes, the first 14 bits are used to indicate the temperature measurement result. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format, as shown in Table 12.

TEMPERATURE (°C) DIGITAL OUTPUT BINARY HEX 128 01 0000 0000 0000 1000 127.96875 00 1111 1111 1111 0FFF 100 00 1100 1000 0000 0C80 75 00 1001 0110 0000 0960 50 00 0110 0100 0000 0640 25 00 0011 0010 0000 0320 0.25 00 0000 0000 1000 0008 0.03125 00 0000 0000 0001 0001 0 00 0000 0000 0000 0000 –0.25 11 1111 1111 1000 3FF8 –25 11 1100 1110 0000 3CE0 –55 11 1001 0010 0000 3920

Table 12. 14-Bit Temperature Data Format

8.3.13.1 Converting from Temperature to Digital Codes

8.3.13.1.1 For Positive Temperatures (for Example, 50°C):

Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code in a 14-bit, left-justified format with the MSB = 0 to denote the positive sign.

Example: 50°C / (0.03125°C per count) = 1600 = 0640h = 00 0110 0100 0000

8.3.13.1.2 For Negative Temperatures (for Example, –25°C):

Generate the twos complement of a negative number by complementing the absolute binary number and adding 1. Then, denote the negative sign with the MSB = 1.

Example: |–25°C| / (0.03125°C per count) = 800 = 0320h = 00 0011 0010 0000

Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000

8.3.13.2 Converting from Digital Codes to Temperature

To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0, simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract 1 from the result and complement all bits. Then, multiply the result by –0.03125°C.

Example: The device reads back 0960h: 0960h has an MSB = 0.

0960h · 0.03125°C = 2400 · 0.03125°C = 75°C

Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.

Subtract 1 and complement the result: 3CE0h → 0320h 0320h · (–0.03125°C) = 800 · (–0.03125°C) = –25°C


8.4 Device Functional Modes

8.4.1 Power-Up and Reset

When the device powers up, a reset is performed. The reset process takes approximately 50 μs. After this power-up reset time, all internal circuitry (including the voltage reference) are stable and communication with the device is possible. As part of the reset process, the device sets all bits in the configuration registers to the respective default settings. By default, the device is set to single-shot mode. After power-up, the device performs a single conversion using the default register settings and then enters a low-power state. When the conversion is complete, the DRDY pin transitions from high to low. The high-to-low transition of the DRDY pin can be used to signal that the ADS1120 is operational and ready to use. The power-up behavior is intended to prevent systems with tight power-supply requirements from encountering a current surge during power-up.

8.4.2 Conversion Modes

The device can be operated in one of two conversion modes that can be selected by the CM bit in the configuration register. These conversion modes are single-shot and continuous conversion mode.

8.4.2.1 Single-Shot Mode

In single-shot mode, the device only performs a conversion when a START/SYNC command is issued. The device consequently performs one single conversion and returns to a low-power state afterwards. The internal oscillator and all analog circuitry (except for the excitation current sources) are turned off while the device waits in this low-power state until the next conversion is started. In addition, every write access to any configuration register also starts a new conversion. Writing to any configuration register while a conversion is ongoing functions as a new START/SYNC command that stops the current conversion and restarts a single new conversion. Each conversion is fully settled (assuming the analog input signal settles to its final value before the conversion starts) because the device digital filter settles within a single cycle.

8.4.2.2 Continuous Conversion Mode

In continuous conversion mode, the device continuously performs conversions. When a conversion completes, the device places the result in the output buffer and immediately begins another conversion.

In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command. The first conversion starts 210 · t(CLK) (normal mode, duty-cycle mode) or 114 · t(CLK) (turbo mode) after the last SCLK falling edge of the START/SYNC command. Writing to any configuration register during an ongoing conversion restarts the current conversion. TI recommends always sending a START/SYNC command immediately after the CM bit is set to 1.


Device Functional Modes (continued)

8.4.3 Operating Modes

In addition to the different conversion modes, the device can also be operated in different operating modes that can be selected to trade-off power consumption, noise performance, and output data rate. These modes are: normal mode, duty-cycle mode, turbo mode, and power-down mode.

8.4.3.1 Normal Mode

Normal mode is the default mode of operation after power-up. In this mode, the internal modulator of the ΔΣ ADC runs at a modulator clock frequency of f(MOD) = f(CLK) / 16, where the system clock (f(CLK)) is either provided by the internal oscillator or the external clock source. The modulator frequency is 256 kHz when using the internal oscillator. Normal mode offers output data rate options ranging from 20 SPS to 1 kSPS with the internal oscillator. The data rate is selected by the DR[2:0] bits in the configuration register. In case an external clock source with a clock frequency other than 4.096 MHz is used, the data rates scale accordingly. For example, using an external clock with f(CLK) = 2.048 MHz yields data rates ranging from 10 SPS to 500 SPS.

8.4.3.2 Duty-Cycle Mode

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator can be averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the device supports an automatic duty-cycle mode that can yield significant power savings by periodically entering a low-power state between conversions. In principle, the device runs in normal mode with a duty cycle of 25%. This functionality means the device performs one conversion in the same manner as when running in normal mode but then automatically enters a low power-state for three consecutive conversion cycles. The noise performance in duty-cycle mode is therefore comparable to the noise performance in normal mode at four times the data rate. Data rates in duty-cycle mode range from 5 SPS to 250 SPS with the internal oscillator.

8.4.3.3 Turbo Mode

Applications that require higher data rates up to 2 kSPS can operate the device in turbo mode. In this mode, the internal modulator runs at a higher frequency of f(MOD) = f(CLK) / 8. f(MOD) equals 512 kHz when the internal oscillator or an external 4.096-MHz clock is used. Note that the device power consumption increases because the modulator runs at a higher frequency. Running the ADS1120 in turbo mode at a comparable output data rate as in normal mode yields better noise performance. For example, the input-referred noise at 90 SPS in turbo mode is lower than the input-referred noise at 90 SPS in normal mode.

8.4.3.4 Power-Down Mode

When the POWERDOWN command is issued, the device enters power-down mode after completing the current conversion. In this mode, all analog circuitry (including the voltage reference and both IDACs) are powered down, the low-side power switch is opened, and the device typically only uses 400 nA of current. While in powerdown mode, the device holds the configuration register settings and responds to commands, but does not perform any data conversions.

Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous conversion mode, depending on the conversion mode selected by the CM bit. Note that writing to any configuration register wakes up the device as well, but only starts a single conversion regardless of the selected conversion mode (CM).


8.5 Programming

8.5.1 Serial Interface

The SPI-compatible serial interface of the device is used to read conversion data, read and write the device configuration registers, and control device operation. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The interface consists of five control lines (CS, SCLK, DIN, DOUT/DRDY, and DRDY) but can be used with only four or even three control signals as well. The dedicated data-ready signal (DRDY) can be configured to be shared with DOUT/DRDY. If the serial bus is not shared with any other device, CS can be tied low permanently so that only signals SCLK, DIN, and DOUT/DRDY are required to communicate with the device.

8.5.1.1 Chip Select (CS)

Chip select (CS) is an active-low input that selects the device for SPI communication. This feature is useful when multiple devices share the same serial bus. CS must remain low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state; as such, DOUT/DRDY cannot indicate when data are ready. In situations where multiple devices are present on the bus, the dedicated DRDY pin can provide an uninterrupted monitor of the conversion status. If the serial bus is not shared with another peripheral, CS can be tied low.

8.5.1.2 Serial Clock (SCLK)

The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data into and out of the device on the DIN and DOUT/DRDY pins, respectively. Even though the input has hysteresis, TI recommends keeping the SCLK signal as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low.

8.5.1.3 Data Ready (DRDY)

DRDY indicates when a new conversion result is ready for retrieval. When DRDY falls low, new conversion data are ready. DRDY transitions back high on the next SCLK rising edge. When no data are read during continuous conversion mode, DRDY remains low but pulses high for a duration of 2 · t(MOD) prior to the next DRDY falling edge. The DRDY pin is always actively driven, even when CS is high.

8.5.1.4 Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data (commands and register data) to the device. The device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin.

8.5.1.5 Data Output and Data Ready (DOUT/DRDY)

DOUT/DRDY serves a dual-purpose function. This pin is used with SCLK to read conversion and register data from the device. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY goes to a highimpedance state when CS is high.

In addition, the DOUT/DRDY pin can also be configured as a data-ready indicator by setting the DRDYM bit high in the configuration register. DOUT/DRDY then transitions low at the same time that the DRDY pin goes low to indicate new conversion data are available. Both signals can be used to detect if new data are ready. However, because DOUT/DRDY is disabled when CS is high, the recommended method of monitoring the end of a conversion when multiple devices are present on the SPI bus is to use the dedicated DRDY pin.

8.5.1.6 SPI Timeout

The ADS1120 offers an SPI timeout feature that can be used to recover communication when a serial interface transmission is interrupted. This feature is especially useful in applications where CS is permanently tied low and is not used to frame a communication sequence. Whenever a complete command is not sent within 13955 · t(MOD) (normal mode, duty-cycle mode) or 27910 · t(MOD) (turbo mode), the serial interface resets and the next SCLK pulse starts a new communication cycle. See the Modulator section for details on the modulator frequency (f(MOD) = 1 / t(MOD)) in the different operating modes. For the RREG and WREG commands, a complete command includes the command byte itself plus the register bytes that are read or written.


Programming (continued)

8.5.2 Data Format

The device provides 16 bits of data in binary twos complement format. The size of one code (LSB) is calculated using Equation 16.

1 LSB =(2 · V_ref / Gain) / 2¹⁶ = +FS / 2¹⁵$ (16)

A positive full-scale input $[V_{IN} \ge (+FS - 1 \ LSB)] = (V_{ref} / Gain - 1 \ LSB)]$ produces an output code of 7FFFh and a negative full-scale input $(V_{IN} \le -FS = -V_{ref} / Gain)$ produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale.

Table 13 summarizes the ideal output codes for different input signals.

Table 13. Ideal Output Code versus Input Signal

(1) Excludes the effects of noise, INL, offset, and gain errors.

Mapping of the analog input signal to the output codes is shown in Figure 60.


Figure 60. Code Transition Diagram

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8.5.3 Commands

The device offers six different commands to control device operation, as shown in Table 14. Four commands are stand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction.

Table 14. Command Definitions

⁽¹⁾ Operands: rr = configuration register (00 to 11), nn = number of bytes – 1 (00 to 11), and x = don't care.

8.5.3.1 RESET (0000 011x)

Resets the device to the default values. Wait at least (50 μs + 32 · t(CLK)) after the RESET command is sent before sending any other command.

8.5.3.2 START/SYNC (0000 100x)

In single-shot mode, the START/SYNC command is used to start a single conversion, or (when sent during an ongoing conversion) to reset the digital filter, and then restarts a single new conversion. When the device is set to continuous conversion mode, the START/SYNC command must be issued one time to start converting continuously. Sending the START/SYNC command while converting in continuous conversion mode resets the digital filter and restarts continuous conversions.

8.5.3.3 POWERDOWN (0000 001x)

The POWERDOWN command places the device into power-down mode. This command shuts down all internal analog components, opens the low-side switch, turns off both IDACs, but holds all register values. In case the POWERDOWN command is issued while a conversion is ongoing, the conversion completes before the ADS1120 enters power-down mode. As soon as a START/SYNC command is issued, all analog components return to their previous states.

8.5.3.4 RDATA (0001 xxxx)

The RDATA command loads the output shift register with the most recent conversion result. This command can be used when DOUT/DRDY or DRDY are not monitored to indicate that a new conversion result is available. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY pin at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded, DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is high.

8.5.3.5 RREG (0010 rrnn)

The RREG command reads the number of bytes specified by nn (number of bytes to be read – 1) from the device configuration register, starting at register address rr. The command is completed after nn + 1 bytes are clocked out after the RREG command byte. For example, the command to read three bytes (nn = 10) starting at configuration register 1 (rr = 01) is 0010 0110.

8.5.3.6 WREG (0100 rrnn)

The WREG command writes the number of bytes specified by nn (number of bytes to be written – 1) to the device configuration register, starting at register address rr. The command is completed after nn + 1 bytes are clocked in after the WREG command byte. For example, the command to write two bytes (nn = 01) starting at configuration register 0 (rr = 00) is 0100 0001. The configuration registers are updated on the last SCLK falling edge.


8.5.4 Reading Data

Output pins\overline{DRDY}$ and $\overline{DQUT}/\overline{DRDY}$ (if the DRDYM bit is set high in the configuration register) transition low when new data are ready for retrieval. The conversion data are written to an internal data buffer. Data can be read directly from this buffer on $\overline{DQUT}/\overline{DQDY}$ when $\overline{DQUT}/\overline{DQDY}falls low without concern of data corruption. An RDATA command does not have to be sent. Data are shifted out on the SCLK rising edges, MSB first, and consist of two bytes of data.

Figure 61 to Figure 63 show the timing diagrams for reading conversion data in continuous conversion mode and single-shot mode when not using the RDATA command.


Figure 63. Single-Shot Mode (DRDYM = 0)

Data can also be read at any time without synchronizing to the\overline{DRDY}$ signal using the RDATA command. When an RDATA command is issued, the conversion result currently stored in the data buffer is shifted out on DOUT/DRDY on the following SCLK rising edges. Data can be read continuously with the RDATA command as an alternative to monitoring $\overline{DRDY}$ or DOUT/ $\overline{DRDY}$ . The $\overline{DRDY}$ pin can be polled after the LSB is clocked out to determine if a new conversion result was loaded. If a new conversion completes during the read operation but $\overline{DRDY}is high. Figure 64 and Figure 65 illustrate the behavior for both cases.

Product Folder Links: ADS1120

DIN

START/SYNC



Figure 64. State of DRDY when a New Conversion Finishes During an RDATA Command


Figure 65. State of DRDY when the Most Recent Conversion Result is Read During an RDATA Command

8.5.5 Sending Commands

The device serial interface is capable of full-duplex operation while reading conversion data when not using the RDATA command. Full-duplex operation means commands are decoded at the same time that conversion data are read. Commands can be sent on any 8-bit data boundary during a data read operation. When a RREG or RDATA command is recognized, the current data read operation is aborted and the conversion data are corrupted, unless the command is sent while the last byte of the conversion result is retrieved. The device starts to output the requested data on DOUT/DRDY at the first SCLK rising edge after the command byte. To read data without interruption, keep DIN low while clocking out data.

A WREG command can be sent without corrupting an ongoing read operation. Figure 66 shows an example for sending a WREG command to write two configuration registers while reading conversion data in continuous conversion mode. After the command is clocked in (after the 32nd SCLK falling edge), the device resets the digital filter and starts converting with the new register settings. The WREG command can be sent on any of the 8-bit boundaries.


Figure 66. Example of Reading Data while Simultaneously Sending a WREG Command

Note that the serial interface does not decode commands while an RDATA or RREG command is executed. That is, all 16 bits of the conversion result must be read after the RDATA command is issued and all requested registers must be read after a RREG command is sent before a new command can be issued.


8.5.6 Interfacing with Multiple Devices

When connecting multiple ADS1120 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective device, DOUT/DRDY enters a 3-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data are available if CS is high, regardless of the DRDYM bit setting in the configuration register. Only the dedicated DRDY pin indicates that new data are available, because the DRDY pin is actively driven even when CS is high.

In some cases the\overline{DRDY}$ pin cannot be interfaced to the microcontroller. This scenario can occur if there are insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated and thus the amount of channels must be limited. Therefore, in order to evaluate when a new conversion of one of the devices is ready, the microcontroller can periodically drop $\overline{CS}$ to the respective device and poll the state of the DOUT/DRDY pin. When $\overline{CS}$ goes low, the DOUT/DRDY pin immediately drives either high or low, provided that the DRDYM bit is configured to 1. If the DOUT/DRDY line drives low, when $\overline{CS}$ is taken low, new data are currently available. If the DOUT/DRDY line drives high, no new data are available. This procedure requires that DOUT/DRDY is high after reading each conversion result and before taking $\overline{CS}high. To make sure DOUT/DRDY is taken high, send 16 additional SCLKs with DIN held low after each data read operation. DOUT/DRDY reads low during the first eight SCLKs after the conversion result is read, and reads high during the following eight SCLKs, as shown in Figure 67. Alternatively, valid data can be retrieved from the device at any time without concern of data corruption by using the RDATA command.


Figure 67. Example of Taking DOUT/DRDY High After Reading a Conversion Result

8.6 Register Map

8.6.1 Configuration Registers

The device has four 8-bit configuration registers that are accessible through the serial interface using the RREG and WREG commands. The configuration registers control how the device operates and can be changed at any time without causing data corruption. After power-up or reset, all registers are set to the default values (which are all 0). All registers retain their values during power-down mode. Table 15 shows the register map of the configuration registers.

Table 15. Configuration Register Map


8.6.1.1 Configuration Register 0 (offset = 00h) [reset = 00h]

Figure 68. Configuration Register 0


LEGEND: R/W = Read/Write; -n = value after reset

Table 16. Configuration Register 0 Field Descriptions


8.6.1.2 Configuration Register 1 (offset = 01h) [reset = 00h]

Figure 69. Configuration Register 1

LEGEND: R/W = Read/Write; -n = value after reset

Table 17. Configuration Register 1 Field Descriptions

Table 18. DR Bit Settings(1)

(1) Data rates provided are calculated using the internal oscillator or an external 4.096-MHz clock. The data rates scale proportionally with the external clock frequency when an external clock other than 4.096 MHz is used.


8.6.1.3 Configuration Register 2 (offset = 02h) [reset = 00h]

Figure 70. Configuration Register 2

Table 19. Configuration Register 2 Field Descriptions

8.6.1.4 Configuration Register 3 (offset = 03h) [reset = 00h]

Figure 71. Configuration Register 3

LEGEND: R/W = Read/Write; -n = value after reset

Table 20. Configuration Register 3 Field Descriptions


9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ADS1120 is a precision, 16-bit,\Delta\SigmaADC that offers many integrated features to ease the measurement of the most common sensor types including various types of temperature and bridge sensors. Primary considerations when designing an application with the ADS1120 include analog input filtering, establishing an appropriate external reference for ratiometric measurements, and setting the common-mode input voltage for the internal PGA. Connecting and configuring the serial interface appropriately is another concern. These considerations are discussed in the following sections.

9.1.1 Serial Interface Connections

The principle serial interface connections for the ADS1120 are shown in Figure 72.


Figure 72. Serial Interface Connections

Most microcontroller SPI peripherals can operate with the ADS1120. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the device can be found in the SPI Timing Requirements section.

TI recommends placing 47-\Omega$ resistors in series with all digital input and output pins ( $\overline{\text{CS}}, SCLK, DIN, DOUT/DRDY, and DRDY). This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines.


9.1.2 Analog Input Filtering

Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and second, to reduce external noise from being a part of the measurement.

As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when frequency components are present in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the actual frequency band of interest below half the sampling frequency. Note that inside a\Delta\Sigma$ ADC, the input signal is sampled at the modulator frequency $f_{(MOD)}$ and not at the output data rate. The filter response of the digital filter repeats at multiples of the sampling frequency ( $f_{(MOD)}), as shown in Figure 73. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any frequency components present in the input signal around the modulator frequency or multiples thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter.




Figure 73. Effect of Aliasing

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Product Folder Links: ADS1120


Many sensor signals are inherently bandlimited; for example, the output of a thermocouple has a limited rate of change. In this case the sensor signal does not alias back into the pass-band when using a\Delta\Sigma$ ADC. However, any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass-band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the measurement result.

A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond $f_{(MOD)}$ / 2 is attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1120 attenuates signals to a certain degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or 10x higher is generally a good starting point for a system design.

Internal to the device, prior to the PGA inputs, is an EMI filter as shown in Figure 39. The cutoff frequency of this filter is approximately 31.8 MHz, which helps reject high-frequency interferences.

9.1.3 External Reference and Ratiometric Measurements

The full-scale range of the ADS1120 is defined by the reference voltage and the PGA gain (FSR = $\pm V_{ref}$ / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to the specific system needs. An external reference must be used if $V_{IN} > 2.048$ V. For example, an external 5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing between 0 V and 5 V.

The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric measurement the same excitation source that is used to excite the sensor is also used to establish the reference for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with the element being measured. The voltage that develops across the reference element is used as the reference source for the ADC. Because current noise and drift are common to both the sensor measurement and the reference, these components cancel out in the ADC transfer function. The output code is only a ratio of the sensor element and the value of the reference resistor. The value of the excitation current source itself is not part of the ADC transfer function.

9.1.4 Establishing a Proper Common-Mode Input Voltage

The ADS1120 can be used to measure various types of input signal configurations: single-ended, pseudo-differential, and fully-differential signals (which can be either unipolar or bipolar). However, configuring the device properly for the respective signal type is important.

Signals where the negative analog input is fixed and referenced to analog ground ( $V_{(AINN)}=0$ V) are commonly called single-ended signals. The common-mode voltage of a single-ended signal consequently varies between 0 V and $V_{IN}/ 2. If the PGA is disabled and bypassed, the common-mode input voltage of the ADS1120 can be as low as 100 mV below AVSS and as large as 100 mV above AVDD. Therefore, the PGA_BYPASS bit must be set in order to measure single-ended signals when a unipolar analog supply is used (AVSS = 0 V). Gains of 1, 2, and 4 are still possible in this configuration. Measuring a 0-mA to 20-mA or 4-mA to 20-mA signal across a load resistor of 100\Omega$ referenced to GND is a typical example. The ADS1120 can directly measure the signal across the load resistor using a unipolar supply, the internal 2.048-V reference, and gain = 1 when the PGA is bypassed.

If gains larger than 4 are needed to measure a single-ended signal, the PGA must be enabled. In this case, a bipolar supply is required for the ADS1120 to meet the common-mode voltage requirement of the PGA.

Signals where the negative analog input (AIN_N) is fixed at a voltage other the 0 V are referred to as pseudo-differential signals. The common-mode voltage of a pseudo-differential signal varies between $V_{(AINN)}$ and $V_{(AINN)} + V_{IN} / 2$ .

Fully-differential signals in contrast are defined as signals having a constant common-mode voltage where the positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.

The ADS1120 can measure pseudo-differential and fully-differential signals both with the PGA enabled or bypassed. However, the PGA must be enabled in order to use gains greater than 4. The common-mode voltage of the input signal must meet the input-common mode voltage restrictions of the PGA (as explained in the PGA Common-Mode Voltage Requirements section) when the PGA is enabled. Setting the common-mode voltage at or near (AVSS + AVDD) / 2 in most cases satisfies the PGA common-mode voltage requirements.

Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals can in general be measured with the ADS1120 using a unipolar analog supply (AVSS = 0 V). As mentioned previously, the PGA must be bypassed in order to measure single-ended, unipolar signals when using a unipolar supply.

A signal is called bipolar when either the positive or negative input can swing below 0 V. A bipolar analog supply (such as AVDD = 2.5 V, AVSS = –2.5 V) is required in order to measure bipolar signals with the ADS1120. A typical application task is measuring a single-ended, bipolar ±10 V signal where AIN^N is fixed at 0 V while AIN^P swings between –10 V and 10 V. The ADS1120 cannot directly measure this signal because the 10 V exceeds the analog power-supply limits. However, one possible solution is to use a bipolar analog supply (AVDD = 2.5 V, AVSS = –2.5 V), gain = 1, and a resistor divider in front of the ADS1120. The resistor divider must divide the voltage down to ≤ ±2.048 V to be able to measure it using the internal 2.048-V reference.

9.1.5 Unused Inputs and Outputs

To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or connect the inputs to mid-supply or to AVDD. AIN3/REFN1 is an exception. Leave the AIN3/REFN1 pin floating when not used in order to avoid accidently shorting the pin to AVSS through the internal low-side switch. Connecting unused analog or reference inputs to AVSS is possible as well, but can yield higher leakage currents than the previously mentioned options.

Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital inputs to the appropriate levels, DVDD or DGND, even when in power-down mode. If CS is not used, tie this pin to DGND. If the internal oscillator is used, tie the CLK pin to DGND. If the DRDY output is not used, leave the pin unconnected or tie the pin to DVDD using a weak pullup resistor.

9.1.6 Pseudo Code Example

The following list shows a pseudo code sequence with the required steps to set up the device and the microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS1120 in continuous conversion mode. The dedicated DRDY pin is used to indicate availability of new conversion data. The default configuration register settings are changed to gain = 16, continuous conversion mode, and simultaneous 50-Hz and 60-Hz rejection.

Power-up;
Delay to allow power supplies to settle and power-up reset to complete; minimum of 50 μs;
Configure the SPI interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA = 1);
If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output;
Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt input;
Set CS to the device low;
Delay for a minimum of td(CSSC);
Send the RESET command (06h) to make sure the device is properly reset after power-up;
Delay for a minimum of 50 μs + 32 · t(CLK);
Write the respective register configuration with the WREG command (43h, 08h, 04h, 10h, and 00h);
As an optional sanity check, read back all configuration registers with the RREG command (23h);
Send the START/SYNC command (08h) to start converting in continuous conversion mode;
Delay for a minimum of td(SCCS);
Clear CS to high (resets the serial interface);
Loop
     {
     Wait for DRDY to transition low;
     Take CS low;
     Delay for a minimum of td(CSSC);
     Send 16 SCLK rising edges to read out conversion data on DOUT/DRDY;
     Delay for for a minimum of td(SCCS);
     Clear CS to high;
     }
Take CS low;
Delay for a minimum of td(CSSC);
Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;
Delay for a minimum of td(SCCS);
Clear CS to high;

TI recommends running an offset calibration before performing any measurements or when changing the gain of the PGA. The internal offset of the device can, for example, be measured by shorting the inputs to mid-supply (MUX[3:1] = 1110). The microcontroller then takes multiple readings from the device with the inputs shorted and stores the average value in the microcontroller memory. When measuring the sensor signal, the microcontroller then subtracts the stored offset value from each device reading to obtain an offset compensated result. Note that the offset can be either positive or negative in value.

9.2 Typical Applications

9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)

Figure 74 shows the basic connections of a thermocouple measurement system when using the internal highprecision temperature sensor for cold-junction compensation. Apart from the thermocouple itself, the only external circuitry required are two biasing resistors, a simple low-pass, antialiasing filter, and the power-supply decoupling capacitors.

Figure 74. Thermocouple Measurement

9.2.1.1 Design Requirements

Table 21. Design Requirements

⁽¹⁾ Not accounting for error of the thermocouple and cold-junction temperature measurement; offset calibration at T(TC) = T(CJ) = 25°C; no gain calibration.

9.2.1.2 Detailed Design Procedure

The biasing resistors RB1 and RB2 are used to set the common-mode voltage of the thermocouple to within the specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). If the application requires the thermocouple to be biased to GND, either a bipolar supply (for example, AVDD = 2.5 V and AVSS = –2.5 V) must be used for the device to meet the common-mode voltage requirement of the PGA, or the PGA must be bypassed. When choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ to 50 MΩ.

In addition to biasing the thermocouple, R_B1 and R_B2 are also useful for detecting an open thermocouple lead. When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AlN0 and AlN1) to AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition.

Although the device digital filter attenuates high-frequency components of noise, TI recommends providing a first-order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by R_F1 , R_F2 , and the differential capacitor C_DIF offers a cutoff frequency that is calculated using Equation 17.

$f_C = 1 / [2π · (R_F1 + R_F2) · C_DIF]$ (17)

Two common-mode filter capacitors ( $C_{M1}$ and $C_{M2}$ ) are also added to offer attenuation of high-frequency, common-mode noise components. TI recommends that the differential capacitor $C_{DIF}$ be at least an order of magnitude (10x) larger than the common-mode capacitors ( $C_{M1}$ and $C_{M2}$ ) because mismatches in the common-mode capacitors can convert common-mode noise into differential noise.

The filter resistors $R_{F1}$ and $R_{F2}$ also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occur. Care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. TI recommends limiting the filter resistor values to below 1 k $\Omega$ .

The filter component values used in this design are: $R_{F1} = R_{F2} = 1 \text{ k}\Omega$ , $C_{DIF} = 100 \text{ nF}$ , and $C_{CM1} = C_{CM2} = 10 \text{ nF}$ .

The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple voltage occurs at $T_{(TC)} = 1250^{\circ}\text{C}$ and is $V_{(TC)} = 50.644$ mV as defined in the tables published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature of $T_{(CJ)} = 0^{\circ}\text{C}$ . A thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. If the cold junction is at a temperature below $0^{\circ}\text{C}$ , the thermocouple produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device. Therefore, the isothermal block temperature is limited to $-40^{\circ}\text{C}$ . A K-type thermocouple at $T_{(TC)} = 1250^{\circ}\text{C}$ produces an output voltage of $V_{(TC)} = 50.644$ mV - (-1.527 mV) = 52.171 mV when referenced to a cold-junction temperature of $T_{(CJ)} = -40^{\circ}\text{C}$ . The maximum gain that can be applied when using the internal 2.048-V reference is then calculated as (2.048 V / 52.171 mV) = 39.3. The next smaller PGA gain setting the device offers is 32.

The device integrates a high-precision temperature sensor that can be used to measure the temperature of the cold junction. To measure the internal temperature of the ADS1120, the device must be set to internal temperature sensor mode by setting the TS bit to 1 in the configuration register. For best performance, careful board layout is critical to achieve good thermal conductivity between the cold junction and the device package.

However, the device does not perform automatic cold-junction compensation of the thermocouple. This compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one or multiple readings of the thermocouple voltage from the device and then sets the device to internal temperature sensor mode (TS = 1) to acquire the temperature of the cold junction. An algorithm similar to the following must be implemented on the microcontroller to compensate for the cold-junction temperature:

• 1. Measure the thermocouple voltage, $V_{(TC)}$ , between AIN0 and AIN1.
• 1. Measure the temperature of the cold junction, $T_{(CJ)}$ , using the temperature sensor mode of the ADS1120.
• 1. Convert the cold-junction temperature into an equivalent thermoelectric voltage, $V_{(CJ)}$ , using the tables or equations provided by NIST.
• 1. Add $V_{(TC)}$ and $V_{(CJ)}$ and translate the summation back into a thermocouple temperature using the NIST tables or equations again.

In some applications, the integrated temperature sensor of the ADS1120 cannot be used (for example, if the accuracy is not high enough or if the device cannot be placed close enough to the cold junction). The additional analog input channels of the device can be used in this case to measure the cold-junction temperature with a thermistor, RTD, or an analog temperature sensor.

The device is capable of 16-bit, noise-free resolution using a gain of 32, the internal 2.048-V reference, and a data rate of 20 SPS (see Table 1 and Table 2). Accordingly the device is able to resolve signals as small as one LSB. The LSB size is calculated using Equation 18:

1 LSB = $(2 · V_ref / Gain) / 2¹⁶ = (2 · 2.048 V / 32) / 2¹⁶ = 1.953 μV(18)


To get an approximation of the achievable temperature resolution per ADC code, the LSB size is divided by the average sensitivity of a K-type thermocouple (41 μV/°C), as shown in Equation 19.

Temperature Resolution per Code = 1.953μ$ V / 41 $\mu$ V/°C = 0.05°C (19)

The register settings for this design are shown in Table 22.

Table 22. Register Settings

9.2.1.3 Application Curves

Figure 75 and Figure 76 show the measurement results. The measurements are taken at $T_A = T_{(CJ)} = 25$ °C. A system offset calibration is performed at $T_{(TC)} = 25^{\circ}$ C, which translates to a $V_{(TC)} = 0$ V when $T_{(CJ)} = 25^{\circ}C. No gain calibration is implemented. The data in Figure 75 are taken using a precision voltage source as the input signal instead of a thermocouple. The respective temperature measurement error in Figure 76 is calculated from the data in Figure 75 using the NIST tables.

The design meets the required temperature measurement accuracy given in Table 21. Note that the measurement error shown in Figure 76 does not include the error of the thermocouple itself and the measurement error of the cold-junction temperature. Those two error sources are in general larger than 0.2°C and therefore, in many cases, dominate the overall system measurement accuracy.



Figure 76. Temperature Measurement Error vs T_(TC)

Copyright © 2013-2017, Texas Instruments Incorporated

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9.2.2 3-Wire RTD Measurement (–200°C to +850°C)

The ADS1120 integrates all necessary features (such as dual-matched programmable current sources, buffered reference inputs, and a PGA) to ease the implementation of ratiometric 2-, 3-, and 4-wire RTD measurements. Figure 77 shows a typical implementation of a ratiometric 3-wire RTD measurement using the excitation current sources integrated in the device to excite the RTD as well as to implement automatic RTD lead-resistance compensation.


Figure 77. 3-Wire RTD Measurement

9.2.2.1 Design Requirements

Table 23. Design Requirements

⁽¹⁾ Not accounting for error of RTD; offset calibration is performed with RRTD = 100 Ω; no gain calibration.

9.2.2.2 Detailed Design Procedure

The circuit in Figure 77 employs a ratiometric measurement approach. In other words, the sensor signal (that is, the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out because these errors are common to both the sensor signal and the reference.


In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision, low-drift reference resistor,R_{REF}$ . The voltage, $V_{ref}$ , generated across the reference resistor (as shown in Equation 20) is used as the ADC reference voltage. Equation 20 reduces to Equation 21 because $I_{IDAC2}$ .

$V_ref = (I_IDAC1 + I_IDAC2) · R_REF$ (20)

$V_ref = 2 · I_IDAC1 · R_REF tag{21}$

To simplify the following discussion, the individual lead resistance values of the RTD ( $R_{LEADx}$ ) are set to zero. Only IDAC1 excites the RTD to produce a voltage ( $V_{RTD}$ ) proportional to the temperature-dependable RTD value and the IDAC1 value, as shown in Equation 22.

$V_RTD = R_{RTD (at temperature)} · I_IDAC1$ (22)

The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage against the reference voltage to produce a digital output code proportional to Equation 23 through Equation 25:

Code $propto V_RTD · Gain / V_ref$ (23)

Code $propto (R_{RTD (at temperature)} · I_IDAC1 · Gain) / (2 · I_IDAC1 · R_REF)$ (24)

$Code propto (R_{RTD (at temperature)} · Gain) / (2 · R_REF)$ (25)

As can be seen from Equation 25, the output code only depends on the value of the RTD, the PGA gain, and the reference resistor ( $R_{REF}$ ), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current therefore does not matter. However, because the value of the reference resistor directly affects the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced by the temperature drift of $R_{REF}$ .

The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance. Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, the differential voltage $(V_{IN})$ across the ADC inputs, AIN0 and AIN1, is calculated using Equation 26:

$V_IN = I_IDAC1 · (R_RTD + R_LEAD1) - I_IDAC2 · R_LEAD2$

$$(26)$$

When $R_{LEAD1} = R_{LEAD2}$ and $I_{IDAC1} = I_{IDAC2}$ , Equation 26 reduces to Equation 27:

$V_IN = I_IDAC1 · R_RTD tag{27}$

In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are well matched.

A first-order differential and common-mode RC filter ( $R_{F1}$ , $R_{F2}$ , $C_{DIF1}$ , $C_{CM1}$ , and $C_{CM2}$ ) is placed on the ADC inputs, as well as on the reference inputs ( $R_{F3}$ , $R_{F4}$ , $C_{DIF2}$ , $C_{CM3}$ , and $C_{CM4}$ ). The same guidelines for designing the input filter apply as described in the Thermocouple Measurement section. For best performance, TI recommends matching the corner frequencies of the input and reference filter. More detailed information on matching the input and reference filter can be found in application report RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 (SBAA201).

The reference resistor R_REF not only serves to generate the reference voltage for the device, but also sets the common-mode voltage of the RTD to within the specified common-mode voltage range of the PGA.

When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs. The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal or less than AVDD – 0.9 V in order to operate accurately. This requirement means that Equation 28 must be met at all times.

$AVSS + I_IDAC1 · (R_LEAD1 + R_RTD) + (I_IDAC1 + I_IDAC2) · (R_LEAD3 + R_REF) ≤ AVDD - 0.9 V$ (28)

The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter resistor values $R_{\text{F1}}$ and $R_{\text{F2}}are small enough and well matched, IDAC1 can be routed to AIN1 and IDAC2 to AIN0 in Figure 77. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured with a single device.


This design example discusses the implementation of a 3-wire Pt100 measurement to be used to measure temperatures ranging from-200^{\circ}\text{C}$ to $+850^{\circ}\text{C}$ as stated in Table 23. The excitation current for the Pt100 is chosen as $I_{\text{IDAC1}} = 500~\mu\text{A}$ , which means a combined current of 1 mA is flowing through the reference resistor, $R_{\text{REF}}$ . As mentioned previously, besides creating the reference voltage for the ADS1120, the voltage across $R_{\text{REF}}$ also sets the common-mode voltage for the RTD measurement. In general, choose the largest reference voltage possible while still maintaining the compliance voltage of the IDACs as well as meeting the common-mode voltage requirement of the PGA. TI recommends setting the common-mode voltage at or near half the analog supply (in this case 3.3 V / 2 = 1.65 V), which in most cases satisfies the common-mode voltage requirements of the PGA. The value for $R_{\text{REF}}$ is then calculated by Equation 29:

$R_REF = V_ref / (I_IDAC1 + I_IDAC2) = 1.65 V / 1 mA = 1.65 kΩ$ (29)

The stability of $R_{REF}$ is critical to achieve good measurement accuracy over temperature and time. Choosing a reference resistor with a temperature coefficient of $\pm 10$ ppm/°C or better is advisable. If a 1.65 k $\Omega$ value is not readily available, another value near 1.65 k $\Omega$ (such as 1.62 k $\Omega$ or 1.69 k $\Omega$ ) can certainly be used as well.

As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured ( $V_{IN}$ (MAX)) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of approximately 391 $\Omega$ as per the NIST tables. The voltage across the Pt100 equates to Equation 30:

$V_{IN (MAX)} = V_{RTD (at 850°C)} = R_{RTD (at 850°C)} · I_IDAC1 = 391 Ω · 500 μA = 195.5 mV$ (30)

The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV) = 8.4. The next smaller PGA gain setting available in the ADS1120 is 8. At a gain of 8, the ADS1120 offers a FSR value as described in Equation 31:

$FSR = ± V_ref / Gain = ± 1.65 V / 8 = ± 206.25 mV$ (31)

This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.

After selecting the values for the IDACs, R_REF, and PGA gain, make sure to double check that the settings meet the common-mode voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the true common-mode voltage at the ADC inputs (AIN0 and AIN1) the lead resistance must be taken into account as well.

The smallest common-mode voltage occurs at the lowest measurement temperature ( $-200^{\circ}$ C) with R_LEADx = 0 $\Omega$ and is calculated using Equation 32 and Equation 33.

$V_{CM (MIN)} = V_ref + (I_IDAC1 + I_IDAC2) · R_LEAD3 + I_IDAC2 · R_LEAD2 + frac{1}{2} I_IDAC1 · R_{RTD (at -200°C)}$

$$(32)$$

$V_{CM (MIN)} = 1.65 V + frac{1}{2} 500 μA · 18.52 Ω = 1.655 V$ (33)

Actually, assuming $V_{CM (MIN)} = V_{ref}$ is a sufficient approximation.

$V_{CM~(MIN)}$ must meet two requirements: Equation 15 requires $V_{CM~(MIN)}$ to be larger than AVDD / 4 = 3.3 V / 4 = 0.825 V and Equation 13 requires $V_{CM~(MIN)}$ to meet Equation 34:

$V_{CM (MIN)} ≥ AVSS + 0.2 V + frac{1}{2} Gain · V_{IN (MAX)} = 0 V + 0.2 V + (frac{1}{2} · 8 · 195.5 mV) = 982 mV$ (34)

Both restrictions are satisfied in this design with a $V_{CM (MIN)} = 1.65 \text{ V}$ .

The largest common-mode voltage occurs at the highest measurement temperature (850°C) and is calculated using Equation 35 and Equation 36.

$V_{CM (MAX)} = V_ref + (I_IDAC1 + I_IDAC2) · R_LEAD3 + I_IDAC2 · R_LEAD2 + frac{1}{2} I_IDAC1 · R_{RTD (at 850^°}C)$ (35)

$V_{CM (MAX)} = 1.65 V + 1 mA · 15 Ω + 500 μ A · 15 Ω + frac{1}{2} 500 μ A · 391 Ω = 1.77 V$ (36)

V_{CM (MAX)} does meet the requirement given by Equation 14, which in this design equates to Equation 37:

$V_{CM (MAX)} ≤ AVDD - 0.2 V - frac{1}{2} Gain · V_{IN (MAX)} = 3.3 V - 0.2 V - (frac{1}{2} · 8 · 195.5 mV) = 2.318 V$ (37)

Finally, the maximum voltage that can occur on input AIN1 must be calculated to determine if the compliance voltage (AVDD -0.9 V = 3.3 V - 0.9 V = 2.4 V) of IDAC1 is met. Note that the voltage on input AIN0 is smaller than the one on input AIN1. Equation 38 and Equation 39 show that the voltage on AIN1 is less than 2.4 V, even when taking the worst-case lead resistance into account.

$V_{AIN1 (MAX)} = V_ref + (I_IDAC1 + I_IDAC2) · R_LEAD3 + I_IDAC1 · (R_{RTD (at 850^°}C) + R_LEAD1)$ (38)

$V_{AIN1 (MAX)} = 1.65 V + 1 mA · 15 Ω + 500 μ A · (391 Ω + 15 Ω) = 1.868 V(39)


The register settings for this design are shown in Table 24.

9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements

Implementing a 2- or 4-wire RTD measurement is very similar to the 3-wire RTD measurement illustrated in Figure 77, except that only one IDAC is required.

Figure 78 shows a typical circuit implementation of a 2-wire RTD measurement. The main difference compared to a 3-wire RTD measurement is with respect to the lead resistance compensation. The voltage drop across the lead resistors, RLEAD1 and RLEAD2, in this configuration is directly part of the measurement (as shown in Equation 40) because there is no means to compensate the lead resistance by use of the second current source. Any compensation must be done by calibration.

V_IN = I_IDAC1 · (R_LEAD1 + R_RTD + R_LEAD2) tag{40}

Figure 78. 2-Wire RTD Measurement


Figure 79 shows a typical circuit implementation of a 4-wire RTD measurement. Similar to the 2-wire RTD measurement, only one IDAC is required for exciting and measuring a 4-wire RTD in a ratiometric manner. The main benefit of using a 4-wire RTD is that the ADC inputs are connected to the RTD in the form of a Kelvin connection. Apart from the input leakage currents of the ADC, there is no current flow through the lead resistorsR_{\text{LEAD2}}$ and $R_{\text{LEAD3}}and therefore no voltage drop is created across them. The voltage at the ADC inputs consequently equals the voltage across the RTD and the lead resistance is of no concern.


Figure 79. 4-Wire RTD Measurement

Note that because only one IDAC is used and flows through the reference resistor,R_{REF}$ , the transfer function of a 2- and 4-wire RTD measurement differs compared to the one of a 3-wire RTD measurement by a factor of 2, as shown in Equation 41.

Code $propto (R_{RTD (at Temperature)} · Gain) / R_REF$ (41)

In addition, the common-mode and reference voltage is reduced compared to the 3-wire RTD configuration. Therefore, some further modifications may be required in case the 3-wire RTD design is used to measure 2- and 4-wire RTDs as well. If the decreased common-mode voltage does not meet the $V_{CM\ (MIN)}$ requirements of the PGA anymore, either increase the value of $R_{REF}by switching in a larger resistor or, alternatively, increase the excitation current while decreasing the gain at the same time.

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9.2.2.3 Application Curves

Figure 80 and Figure 81 show the measurement results. The measurements are taken at T^A = 25°C. A system offset calibration is performed using a reference resistor of 100 Ω. No gain calibration is implemented. The data in Figure 80 are taken using precision resistors instead of a 3-wire Pt100. The respective temperature measurement error in Figure 81 is calculated from the data in Figure 80 using the NIST tables.

The design meets the required temperature measurement accuracy given in Table 23. Note that the measurement error shown in Figure 81 does not include the error of the RTD itself.



Figure 80. Resistance Measurement Error vs RRTD Figure 81. Temperature Measurement Error vs T(RTD)


9.2.3 Resistive Bridge Measurement

The device offers several features to ease the implementation of ratiometric bridge measurements (such as a PGA with gains up to 128, buffered, differential reference inputs, and a low-side power switch).


Figure 82. Resistive Bridge Measurement

9.2.3.1 Design Requirements

Table 25. Design Requirements

9.2.3.2 Detailed Design Procedure

To implement a ratiometric bridge measurement, the bridge excitation voltage is simultaneously used as the reference voltage for the ADC; see Figure 82. With this configuration, any drift in excitation voltage also shows up on the reference voltage, consequently canceling out drift error. Either of the two device reference input pairs can be connected to the bridge excitation voltage. However, only the negative reference input (REFN1) can be internally routed to a low-side power switch. By connecting the low side of the bridge to REFN1, the device can automatically power-down the bridge by opening the low-side power switch. When the PSW bit in the configuration register is set to 1, the device opens the switch every time a POWERDOWN command is issued and closes the switch again when a START/SYNC command is sent.

The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal use of the ADC full-scale range. Using a symmetrical bridge with the excitation voltage equal to the supply voltage of the device ensures that the output signal of the bridge meets the common-mode voltage requirement of the PGA.


Note that the maximum input voltage of ADS1120 is limited toV_{IN\ (MAX)} = \pm[(AVDD-AVSS)-0.4\ V]$ / Gain, which means the entire full-scale range, FSR = $\pm(AVDD-AVSS)$ / Gain, cannot be used in this configuration. This limitation is a result of the output drive capability of the PGA amplifiers (A1 and A2); see Figure 39. The output of each amplifier must stay 200 mV away from the rails (AVDD and AVSS), otherwise the PGA becomes nonlinear. Consequently, the maximum output swing of the PGA is limited to $V_{OUT} = \pm[(AVDD-AVSS)-0.4\ V]$ .

Using a 2-mV/V load cell with a 5-V excitation yields a maximum differential output voltage of $V_{IN~(MAX)} = \pm 10~mV$ , which meets Equation 42 when using a gain of 128.

$V_{IN (MAX)} ≤ ± [(AVDD - AVSS) - 0.4 V] / Gain = ± (5 V - 0.4 V) / 128 = ± 36 mV$ (42)

A first-order differential and common-mode RC filter ( $R_{F1}$ , $R_{F2}$ , $C_{DIF1}$ , $C_{CM1}$ , and $C_{CM2}$ ) is placed on the ADC inputs. The reference has an additional capacitor $C_{DIF2}$ to limit reference noise. Care must be taken to maintain a limited amount of filtering or the measurement will no longer be ratiometric.

The device is capable of 16-bit, noise-free resolution using a gain of 128 at 20 SPS for the specified reference voltage. Accordingly the device is able to resolve signals as small as one LSB. The LSB size is calculated using Equation 43:

1 LSB = $(2 · V_ref / Gain) / 2¹⁶ = (2 · 5.0 V / 128) / 2¹⁶ = 1.192 μV$ (43)

To find the total number of counts available for the bridge measurement, the maximum output voltage is divided by the LSB value. Dividing 10 mV by 1.192 $\mu$ V equates to 8389 total counts available, which meets the design parameter of 8000 counts.

The register settings for this design are shown in Table 26.

Table 26. Register Settings

Minimum and maximum specifications apply from T^A = –40°C to +125°C. Typical specifications are at T^A = 25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external Vref = 2.5 V (unless otherwise noted).(1)

⁽²⁾ Minimum and maximum values are ensured by design and characterization data.

⁽¹⁾ Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

over operating ambient temperature range (unless otherwise noted)

⁽¹⁾ AIN^P and AIN^N denote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs. PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case. See the Bypassing the PGA section for more information.

⁽²⁾ Excluding the effects of offset and gain error. Limited to ±[(AVDD – AVSS) – 0.4 V] / Gain, when the PGA is enabled.

⁽³⁾ REFPx and REFNx denote one of two available differential reference input pairs.