AD9361BBCZ-REEL

[AD9361](https://www.analog.com/ad9361)

Manufacturer

Analog Devices Inc.

Overview

Part: AD9361 from Analog Devices

Type: RF Agile Transceiver

Key Specs:

TX band: 47 MHz to 6.0 GHz
RX band: 70 MHz to 6.0 GHz
Tunable channel bandwidth: <200 kHz to 56 MHz
Receiver noise figure: 2 dB at 800 MHz LO
Transmitter EVM: ≤-40 dB
Transmitter noise floor: ≤-157 dBm/Hz
Local oscillator step size: 2.4 Hz maximum
Receiver gain range: 0 dB (minimum) to 74.5 dB (maximum at 800 MHz)
Received Signal Strength Indicator (RSSI) range: 100 dB
Receiver noise figure at 2.4 GHz: 3 dB

Features:

RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
Supports TDD and FDD operation
Dual receivers: 6 differential inputs
Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz LO
RX gain control: Real-time monitor and control signals for manual gain, Independent automatic gain control
Dual transmitters: 4 differential outputs
Highly linear broadband transmitter: TX EVM: ≤-40 dB, TX noise: ≤-157 dBm/Hz noise floor, TX monitor: ≥66 dB dynamic range with 1 dB accuracy
Integrated fractional-N synthesizers: 2.4 Hz maximum local oscillator (LO) step size
Multichip synchronization
CMOS/LVDS digital interface

Applications:

Point to point communication systems
Femtocell/picocell/microcell base stations
General-purpose radio systems

Package:

144-ball chip scale package ball grid array (CSP_BGA): 10 mm × 10 mm

Features

► RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
► TX band: 47 MHz to 6.0 GHz
► RX band: 70 MHz to 6.0 GHz
► Supports TDD and FDD operation
► Tunable channel bandwidth: <200 kHz to 56 MHz
► Dual receivers: 6 differential inputs
► Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz LO
► RX gain control
- ► Real-time monitor and control signals for manual gain
- ► Independent automatic gain control
► Dual transmitters: 4 differential outputs
► Highly linear broadband transmitter
- ► TX EVM: ≤-40 dB
- ► TX noise: ≤-157 dBm/Hz noise floor
- ► TX monitor: ≥66 dB dynamic range with 1 dB accuracy
► Integrated fractional-N synthesizers
- ► 2.4 Hz maximum local oscillator (LO) step size
► Multichip synchronization
► CMOS/LVDS digital interface

Applications

► Point to point communication systems
► Femtocell/picocell/microcell base stations
► General-purpose radio systems

Pin Configuration

Pin No.	Type1	Mnemonic	Description
A1, A2	I	RX2A_N, RX2A_P	Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a single-ended input or combined to make a differential pair. Tie unused pins to ground.
A3, M3	NC	NC	No Connect. Do not connect to these pins.
A4, A6, B1, B2, B12, C2, C7 to C12, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6	I	VSSA	Analog Ground. Tie these pins directly to the VSSD digital ground on the printed circuit board (one ground plane).
A5	I	TX_MON2	Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground.
A7, A8	O	TX2A_N, TX2A_P	Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V.
A9, A10	O	TX2B_N, TX2B_P	Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V.
A11	I	VDDA1P1_TX_VCO	Transmit VCO Supply Input. Connect to B11.
A12	I	TX_EXT_LO_IN	External Transmit LO Input. If this pin is unused, tie it to ground.
B3	O	AUXDAC1	Auxiliary DAC 1 Output.
B4 to B7	O	GPO_3 to GPO_0	3.3 V Capable General-Purpose Outputs.
B8	I	VDD_GPO	2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V.
B9	I	VDDA1P3_TX_LO	Transmit LO 1.3 V Supply Input.
B10	I	VDDA1P3_TX_VCO_LDO	Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
B11	O	TX_VCO_LDO_OUT	Transmit VCO LDO Output. Connect to A11 and a 1 μF bypass capacitor in series with a 1 Ω resistor to ground.
C1, D1	I	RX2C_P, RX2C_N	Receive Channel 2 Differential Input C. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground.
C3	O	AUXDAC2	Auxiliary DAC 2 Output.
C4	I	TEST/ENABLE	Test Input. Ground this pin for normal operation.
C5, C6, D6, D5	I	CTRL_IN0 to CTRL_IN3	Control Inputs. Used for manual RX gain and TX attenuation control.
D2	I	VDDA1P3_RX_RF	Receiver 1.3 V Supply Input. Connect to D3.
D3	I	VDDA1P3_RX_TX	1.3 V Supply Input.
D4, E4 to E6, F4 to F6, G4	O	CTRL_OUT0, CTRL_OUT1 to CTRL_OUT3, CTRL_OUT6 to CTRL_OUT4, CTRL_OUT7	Control Outputs. These pins are multipurpose outputs that have programmable functionality.

Absolute Maximum Ratings

Table 11.

Parameter	Rating
VDDx to VSSx	-0.3 V to +1.4 V
VDD_INTERFACE to VSSx	-0.3 V to +3.0 V
VDD_GPO to VSSx	-0.3 V to +3.9 V
Logic Inputs and Outputs to VSSx	-0.3 V to VDD_INTERFACE + 0.3 V
Input Current to Any Pin Except Supplies	±10 mA
RF Inputs (Peak Power)	2.5 dBm
TX Monitor Input Power (Peak Power)	9 dBm
Package Power Dissipation	(TJMAX - TA)/θJA
Maximum Junction Temperature (TJMAX)	110°C
Operating Temperature Range	-40°C to +85°C
Storage Temperature Range	-65°C to +150°C

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Thermal Information

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Package Type
144-Ball
CSP_BGA

¹ Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.

² Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³ Per MIL-STD 883, Method 1012.1.

⁴ Per JEDEC JESD51-8 (still air).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

	1	2	3	4	5	6	7	8	9	10	11	12
A	RX2A N	RX2A P	NC	VSSA	TX MON2	VSSA	TX2A N	TX2A P	TX2B N	TX2B P	VDDA1P1 TX VCO	TX EXT LO IN
B	VSSA	VSSA	AUXDAC1	GPO 3	GPO 2	GPO 1	GPO 0	VDD GPO	VDDA1P3 TX LO	VDDA1P3 TX VCO LDO	TX VCO LDO OUT	VSSA
C	RX2C P	VSSA	AUXDAC2	TEST/ ENABLE	CTRL IN0	CTRL IN1	VSSA	VSSA	VSSA	VSSA	VSSA	VSSA
D	RX2C N	VDDA1P3 RX RF	VDDA1P3 RX TX	CTRL OUT0	CTRL IN3	CTRL IN2	P0 D9/ TX D4 P	P0 D7/ TX D3 P	P0 D5/ TX D2 P	P0 D3/ TX D1 P	P0 D1/ TX D0 P	VSSD
E	RX2B P	VDDA1P3 RX LO	VDDA1P3 TX LO BUFFER	CTRL OUT1	CTRL OUT2	CTRL OUT3	P0 D11/ TX D5 P	P0 D8/ TX D4 N	P0 D6/ TX D3 N	P0 D4/ TX D2 N	P0 D2/ TX D1 N	P0 D0/ TX D0 N
F	RX2B N	VDDA1P3 RX VCO LDO	VSSA	CTRL OUT6	CTRL OUT5	CTRL OUT4	VSSD	P0 D10/ TX D5 N	VSSD	FB CLK P	VSSD	VDDD1P3 DIG
G	RX EXT LO IN	RX VCO LDO OUT	VDDA1P1 RX VCO	CTRL OUT7	EN AGC	ENABLE	RX FRAME N	RX FRAME P	TX FRAME P	FB CLK N	DATA CLK P	VSSD
H	RX1B P	VSSA	VSSA	TXNRX	SYNC IN	VSSA	VSSD	P1 D11/ RX D5 P	TX FRAME N	VSSD	DATA CLK N	VDD INTERFACE
J	RX1B N	VSSA	VDDA1P3 RX SYNTH	SPI D	SPI CLK	CLK OUT	P1 D10/ RX D5 N	P1 D9/ RX D4 P	P1 D7/ RX D3 P	P1 D5/ RX D2 P	P1 D3/ RX D1 P	P1 D1/ RX D0 P
K	RX1C P	VSSA	VDDA1P3 TX SYNTH	VDDA1P3 BB	RESETB	SPI ENB	P1 D8/ RX D4 N	P1 D6/ RX D3 N	P
Figure 2. Pin Configuration, Top View

Table 13. Pin Function Descriptions

Pin No.	Type1	Mnemonic	Description
A1, A2	I	RX2A_N, RX2A_P	Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a single-ended input or combined to make a differential pair. Tie unused pins to ground.
A3, M3	NC	NC	No Connect. Do not connect to these pins.
A4, A6, B1, B2, B12, C2, C7 to C12, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6	I	VSSA	Analog Ground. Tie these pins directly to the VSSD digital ground on the printed circuit board (one ground plane).
A5	I	TX_MON2	Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground.
A7, A8	O	TX2A_N, TX2A_P	Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V.
A9, A10	O	TX2B_N, TX2B_P	Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V.
A11	I	VDDA1P1_TX_VCO	Transmit VCO Supply Input. Connect to B11.
A12	I	TX_EXT_LO_IN	External Transmit LO Input. If this pin is unused, tie it to ground.
B3	O	AUXDAC1	Auxiliary DAC 1 Output.
B4 to B7	O	GPO_3 to GPO_0	3.3 V Capable General-Purpose Outputs.
B8	I	VDD_GPO	2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V.
B9	I	VDDA1P3_TX_LO	Transmit LO 1.3 V Supply Input.
B10	I	VDDA1P3_TX_VCO_LDO	Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
B11	O	TX_VCO_LDO_OUT	Transmit VCO LDO Output. Connect to A11 and a 1 μF bypass capacitor in series with a 1 Ω resistor to ground.
C1, D1	I	RX2C_P, RX2C_N	Receive Channel 2 Differential Input C. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground.
C3	O	AUXDAC2	Auxiliary DAC 2 Output.
C4	I	TEST/ENABLE	Test Input. Ground this pin for normal operation.
C5, C6, D6, D5	I	CTRL_IN0 to CTRL_IN3	Control Inputs. Used for manual RX gain and TX attenuation control.
D2	I	VDDA1P3_RX_RF	Receiver 1.3 V Supply Input. Connect to D3.
D3	I	VDDA1P3_RX_TX	1.3 V Supply Input.
D4, E4 to E6, F4 to F6, G4	O	CTRL_OUT0, CTRL_OUT1 to CTRL_OUT3, CTRL_OUT6 to CTRL_OUT4, CTRL_OUT7	Control Outputs. These pins are multipurpose outputs that have programmable functionality.

Table 13. Pin Function Descriptions (Continued)

Pin No.	Type1	Mnemonic	Description
D7	I/O	P0_D9/TX_D4_P	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
D8	I/O	P0_D7/TX_D3_P	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
D9	I/O	P0_D5/TX_D2_P	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
D10	I/O	P0_D3/TX_D1_P	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
D11	I/O	P0_D1/TX_D0_P	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
D12, F7, F9, F11, G12, H7, H10, K12	I	VSSD	Digital Ground. Tie these pins directly to the VSSA analog ground on the printed circuit board (one ground plane).
E1, F1	I	RX2B_P, RX2B_N	Receive Channel 2 Differential Input B. Each pin can be used as a single-ended input or combined to make a differential pair. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground.
E2	I	VDDA1P3_RX_LO	Receive LO 1.3 V Supply Input.
E3	I	VDDA1P3_TX_LO_BUFFER	1.3 V Supply Input.
E7	I/O	P0_D11/TX_D5_P	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS 6‑bit TX differential input bus with internal LVDS termination.
E8	I/O	P0_D8/TX_D4_N	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
E9	I/O	P0_D6/TX_D3_N	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
E10	I/O	P0_D4/TX_D2_N	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
E11	I/O	P0_D2/TX_D1_N	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
E12	I/O	P0_D0/TX_D0_N	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS 6-bit TX differential input bus with internal LVDS termination.
F2	I	VDDA1P3_RX_VCO_LDO	Receive VCO LDO 1.3 V Supply Input. Connect to E2.
F8	I/O	P0_D10/TX_D5_N	Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin. As P0_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 0. Alternatively, this pin (TX_D5_N) can function as part of the LVDS 6‑bit TX differential input bus with internal LVDS termination.
F10, G10	I	FB_CLK_P, FB_CLK_N	Feedback Clock. These pins receive the FB_CLK signal that clocks in TX data. In CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.
F12	I	VDDD1P3_DIG	1.3 V Digital Supply Input.
G1	I	RX_EXT_LO_IN	External Receive LO Input. If this pin is unused, tie it to ground.
G2	O	RX_VCO_LDO_OUT	Receive VCO LDO Output. Connect this pin directly to G3 and a 1 μF bypass capacitor in series with a 1 Ω resistor to ground.
G3	I	VDDA1P1_RX_VCO	Receive VCO Supply Input. Connect this pin directly to G2 only.

Table 13. Pin Function Descriptions (Continued)

Pin No.	Type1	Mnemonic	Description
G5	I	EN_AGC	Manual Control Input for Automatic Gain Control (AGC).
G6	I	ENABLE	Control Input. This pin moves the device through various operational states.
G7, G8	O	RX_FRAME_N, RX_FRAME_P	Receive Digital Data Framing Output Signal. These pins transmit the RX_FRAME signal that indicates whether the RX output data is valid. In CMOS mode, use RX_FRAME_P as the output and leave RX_FRAME_N unconnected.
G9, H9	I	TX_FRAME_P, TX_FRAME_N	Transmit Digital Data Framing Input Signal. These pins receive the TX_FRAME signal that indicates when TX data is valid. In CMOS mode, use TX_FRAME_P as the input and tie TX_FRAME_N to ground.
G11, H11	O	DATA_CLK_P, DATA_CLK_N	Receive Data Clock Output. These pins transmit the DATA_CLK signal that is used by the BBP to clock RX data. In CMOS mode, use DATA_CLK_P as the output and leave DATA_CLK_N unconnected.
H1, J1	I	RX1B_P, RX1B_N	Receive Channel 1 Differential Input B. Alternatively, each pin can be used as a single-ended input. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground.
H4	I	TXNRX	Enable State Machine Control Signal. This pin controls the data port bus direction. Logic low selects the RX direction, and logic high selects the TX direction.
H5	I	SYNC_IN	Input to Synchronize Digital Clocks Between Multiple AD9361 Devices. If this pin is unused, tied it to ground.
H8	I/O	P1_D11/RX_D5_P	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D5_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
H12	I	VDD_INTERFACE	1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).
J3	I	VDDA1P3_RX_SYNTH	1.3 V Supply Input.
J4	I	SPI_DI	SPI Serial Data Input.
J5	I	SPI_CLK	SPI Clock Input.
J6	O	CLK_OUT	Output Clock. This pin can be configured to output either a buffered version of the external input clock, the DCXO, or a divided-down version of the internal ADC_CLK.
J7	I/O	P1_D10/RX_D5_N	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D5_N) can function as part of the LVDS 6‑bit RX differential output bus with internal LVDS termination.
J8	I/O	P1_D9/RX_D4_P	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D4_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
J9	I/O	P1_D7/RX_D3_P	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D3_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
J10	I/O	P1_D5/RX_D2_P	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D2_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
J11	I/O	P1_D3/RX_D1_P	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
J12	I/O	P1_D1/RX_D0_P	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
K1, L1	I	RX1C_P, RX1C_N	Receive Channel 1 Differential Input C. Alternatively, each pin can be used as a single-ended input. These inputs experience degraded performance above 3 GHz. Tie unused pins to ground.
K3	I	VDDA1P3_TX_SYNTH	1.3 V Supply Input.

Table 13. Pin Function Descriptions (Continued)

Pin No.	Type1	Mnemonic	Description
K4	I	VDDA1P3_BB	1.3 V Supply Input.
K5	I	RESETB	Asynchronous Reset. Logic low resets the device.
K6	I	SPI_ENB	SPI Enable Input. Set this pin to logic low to enable the SPI bus.
K7	I/O	P1_D8/RX_D4_N	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
K8	I/O	P1_D6/RX_D3_N	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
K9	I/O	P1_D4/RX_D2_N	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
K10	I/O	P1_D2/RX_D1_N	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
K11	I/O	P1_D0/RX_D0_N	Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit RX differential output bus with internal LVDS termination.
L4	I	RBIAS	Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor to ground.
L5	I	AUXADC	Auxiliary ADC Input. If this pin is unused, tie it to ground.
L6	O	SPI_DO	SPI Serial Data Output in 4-Wire Mode, or High-Z in 3-Wire Mode.
M1, M2	I	RX1A_P, RX1A_N	Receive Channel 1 Differential Input A. Alternatively, each pin can be used as a single-ended input. Tie unused pins to ground.
M5	I	TX_MON1	Transmit Channel 1 Power Monitor Input. When this pin is unused, tie it to ground.
M7, M8	O	TX1A_P, TX1A_N	Transmit Channel 1 Differential Output A. Tie unused pins to 1.3 V.
M9, M10	O	TX1B_P, TX1B_N	Transmit Channel 1 Differential Output B. Tie unused pins to 1.3 V.
M11, M12	I	XTALP, XTALN	Reference Frequency Crystal Connections. When a crystal is used, connect it between these two pins. When an external clock source is used, connect it to XTALN and leave XTALP unconnected.

800 MHZ FREQUENCY BAND

Figure 3. RX Noise Figure vs. RF Frequency

Figure 4. RSSI Error vs. RX Input Power, LTE 10 MHz Modulation (Referenced to -50 dBm Input Power at 800 MHz)

Figure 5. RSSI Error vs. RX Input Power, Edge Modulation (Referenced to -50 dBm Input Power at 800 MHz)

Figure 6. RX EVM vs. RX Input Power, 64 QAM LTE 10 MHz Mode, 19.2 MHz REF_CLK

Figure 7. RX EVM vs. RX Input Power, GSM Mode, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 8. RX EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = -82 dBm, 5 MHz OFDM Blocker at 7.5 MHz Offset

Figure 9. RX EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with PIN = -90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset

Figure 10. RX Noise Figure vs. Interferer Power Level, Edge Signal of Interest with PIN = -90 dBm, CW Blocker at 3 MHz Offset, Gain Index = 64

Figure 11. RX Gain vs. RX LO Frequency, Gain Index = 76 (Maximum Setting)

Figure 12. Third-Order Input Intercept Point (IIP3) vs. RX Gain Index, f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode

Figure 13. Second-Order Input Intercept Point (IIP2) vs. RX Gain Index, f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode

Figure 14. RX Local Oscillator (LO) Leakage vs. RX LO Frequency

Figure 15. RX Emission at LNA Input, DC to 12 GHz, fLO_RX = 800 MHz, LTE 10 MHz, fLO_TX = 860 MHz

Figure 16. TX Output Power vs. TX LO Frequency, Attenuation Setting = 0 dB, Single Tone Output

Figure 17. TX Power Control Linearity Error vs. Attenuation Setting

Figure 18. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown)

Figure 19. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 3 MHz Range

Figure 20. TX Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX = 800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 12 MHz Range

Figure 21. TX EVM vs. TX Attenuation Setting, fLO_TX = 800 MHz, LTE 10 MHz, 64 QAM Modulation, 19.2 MHz REF_CLK

Figure 22. TX EVM vs. TX Attenuation Setting, fLO_TX = 800 MHz, GSM Modulation, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 23. Integrated TX LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK

Figure 24. Integrated TX LO Phase Noise vs. Frequency, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 25. TX Carrier Rejection vs. Frequency

Figure 26. TX Second-Order Harmonic Distortion (HD2) vs. Frequency

Figure 27. TX Third-Order Harmonic Distortion (HD3) vs. Frequency

Figure 28. TX Third-Order Output Intercept Point (OIP3) vs. TX Attenuation Setting

Figure 29. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset

Figure 30. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, GSM Signal of Interest with Noise Measured at 20 MHz Offset

Figure 31. TX Single Sideband (SSB) Rejection vs. Frequency, 1.5375 MHz Offset

2.4 GHZ FREQUENCY BAND

Figure 32. RX Noise Figure vs. RF Frequency

Figure 33. RSSI Error vs. RX Input Power, Referenced to -50 dBm Input Power at 2.4 GHz

Figure 34. RX EVM vs. Input Power, 64 QAM LTE 20 MHz Mode, 40 MHz REF_CLK

Figure 35. RX EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = -75 dBm, LTE 20 MHz Blocker at 20 MHz Offset

Figure 36. RX EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest with PIN = -75 dBm, LTE 20 MHz Blocker at 40 MHz Offset

Figure 37. RX Gain vs. RX LO Frequency, Gain Index = 76 (Maximum Setting)

Figure 38. Third-Order Input Intercept Point (IIP3) vs. RX Gain Index,f1 = 30 MHz, f2 = 61 MHz

Figure 39. Second-Order Input Intercept Point (IIP2) vs. RX Gain Index, f1 = 60 MHz, f2 = 61 MHz

Figure 40. RX Local Oscillator (LO) Leakage vs. RX LO Frequency

Figure 41. RX Emission at LNA Input, DC to 12 GHz, fLO_RX = 2.4 GHz, LTE 20 MHz, fLO_TX = 2.46 GHz

Figure 42. TX Output Power vs. TX LO Frequency, Attenuation Setting = 0 dB, Single Tone Output

Figure 43. TX Power Control Linearity Error vs. Attenuation Setting

Figure 45. TX EVM vs. Transmitter Attenuation Setting, 40 MHz REF_CLK, LTE 20 MHz, 64 QAM Modulation

Figure 46. Integrated TX LO Phase Noise vs. Frequency, 40 MHz REF_CLK

Figure 48. TX Second-Order Harmonic Distortion (HD2) vs. Frequency

Figure 49. TX Third-Order Harmonic Distortion (HD3) vs. Frequency

Figure 50. TX Third-Order Output Intercept Point (OIP3) vs. TX Attenuation Setting

Figure 51. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset

Figure 52. TX Single Sideband (SSB) Rejection vs. Frequency, 3.075 MHz Offset

5.5 GHZ FREQUENCY BAND

Figure 53. RX Noise Figure vs. RF Frequency

Figure 54. RSSI Error vs. RX Input Power, Referenced to -50 dBm Input Power at 5.8 GHz

Figure 55. RX EVM vs. RX Input Power, 64 QAM WiMAX 40 MHz Mode, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 56. RX EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = -74 dBm, WiMAX 40 MHz Blocker at 40 MHz Offset

Figure 57. RX EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest with PIN = -74 dBm, WiMAX 40 MHz Blocker at 80 MHz Offset

Figure 58. RX Gain vs. Frequency, Gain Index = 76 (Maximum Setting)

Figure 59. Third-Order Input Intercept Point (IIP3) vs. RX Gain Index,f1 = 50 MHz, f2 = 101 MHz

Figure 60. Second-Order Input Intercept Point (IIP2) vs. RX Gain Index, f1 = 70 MHz, f2 = 71 MHz

Figure 61. RX Local Oscillator (LO) Leakage vs. Frequency

Figure 62. RX Emission at LNA Input, DC to 26 GHz, fLO_RX = 5.8 GHz, WiMAX 40 MHz

Figure 63. TX Output Power vs. Frequency, Attenuation Setting = 0 dB, Single Tone

Figure 64. TX Power Control Linearity Error vs. Attenuation Setting

Figure 66. TX EVM vs. TX Attenuation Setting, WiMAX 40 MHz, 64 QAM Modulation, fLO_TX = 5.495 GHz, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 67. Integrated TX LO Phase Noise vs. Frequency, 40 MHz REF_CLK (Doubled Internally for RF Synthesizer)

Figure 68. TX Carrier Rejection vs. Frequency

Figure 69. TX Second-Order Harmonic Distortion (HD2) vs. Frequency

Figure 70. TX Third-Order Harmonic Distortion (HD3) vs. Frequency

Figure 71. TX Third-Order Output Intercept Point (OIP3) vs. TX Attenuation Setting, fLO_TX = 5.8 GHz

Figure 72. TX Signal-to-Noise Ratio (SNR) vs. TX Attenuation Setting, WiMAX 40 MHz Signal of Interest with Noise Measured at 90 MHz Offset, fLO_TX = 5.745 GHz

Figure 73. TX Single Sideband (SSB) Rejection vs. Frequency, 7 MHz Offset

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
AD9361	Analog Devices Inc.	—
AD9361BBCZ	Analog Devices Inc.	144-LFBGA, CSPBGA

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