AD8605

Part: AD8605/AD8606/AD8608 from Analog Devices

Type: Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers

Key Specs:

• Low offset voltage: 65 μV maximum
• Low input bias currents: 1 pA maximum
• Low noise: 8 nV/√Hz
• Wide bandwidth: 10 MHz
• High open-loop gain: 1000 V/mV
• Single-supply operation: 2.7 V to 5.5 V

Features:

• Unity gain stable
• Rail-to-rail input and output
• Single, dual, and quad amplifier variants
• Analog Devices, Inc. patented DigiTrim® trimming technique
• Specified over the extended industrial temperature range (-40°C to +125°C)

Applications:

• Photodiode amplification
• Battery-powered instrumentation
• Multipole filters
• Sensors
• Barcode scanners
• Audio
• Optical control loops
• Portable and loop-powered instrumentation
• Audio amplification for portable devices
• Filters
• Integrators
• High impedance sensors

Package:

• AD8605: 5-lead SOT-23, 5-ball WLCSP
• AD8606: 8-lead MSOP, 8-ball WLSCP, narrow SOIC
• AD8608: 14-lead TSSOP, narrow 14-lead SOIC

Low offset voltage: 65 μV maximum Low input bias currents: 1 pA maximum

Low noise: 8 nV/√Hz Wide bandwidth: 10 MHz

High open-loop gain: 1000 V/mV

Unity gain stable

Single-supply operation: 2.7 V to 5.5 V

5-ball WLCSP for single (AD8605) and 8-ball WLCSP for

dual (AD8606)

Photodiode amplification Battery-powered instrumentation Multipole filters Sensors Barcode scanners Audio

Figure 1. 5-Lead SOT-23 (RJ Suffix)

Figure 2. 8-Ball WLCSP (CB Suffix)

Figure 3. 5-Ball WLCSP (CB Suffix)

Figure 4. 14-Lead SOIC_N (R Suffix)

Figure 5. 8-Lead MSOP (RM Suffix), 8-Lead SOIC_N (R Suffix)

Figure 6. 14-Lead TSSOP (RU Suffix)

^<sup>1 Protected by U.S. Patent No. 5,969,657.

| TABLE OF CONTENTS | |--------------------------------------------------------------|------------------------------------------------------------| | Features 1 | THD + Noise 16 | | Applications 1 | Total Noise Including Source Resistors 17 | | General Description 1 | Channel Separation 17 | | Pin Configurations 1 | Capacitive Load Drive 17 | | Revision History 2 | Light Sensitivity 18 | | 5 V Electrical Specifications 4 | WLCSP Assembly Considerations 18 | | 2.7 V Electrical Specifications 6 | I-V Conversion Applications 19 | | Absolute Maximum Ratings 8 | Photodiode Preamplifier Applications 19 | | ESD Caution 8 | Audio and PDA Applications 19 | | Typical Performance Characteristics 9 | Instrumentation Amplifiers 20 | | Applications Information 16 | DAC Conversion 20 | | Output Phase Reversal 16 | Outline Dimensions 21 | | Maximum Power Dissipation 16 | Ordering Guide 24 | | Input Overvoltage Protection 16 | | REVISION HISTORY | | 11/2017—Rev. N to Rev. O | 9/2008—Rev. H to Rev. I | | Added Figure 44 and Figure 45; Renumbered Sequentially 15 | Changes to Input Overvoltage Protection Section 15 | | Changes to Figure 51 17 | Changes to Ordering Guide 22 | | Changes to Ordering Guide 24 | 2/2008—Rev. G to Rev. H | | 4/2013—Rev. M to Rev. N | Changes to Features 1 | | Changes to Input Overvoltage Section and THD + Noise | Changes to Table 1 4 | | Section 16 | Changes to Table 2 6 | | Changes to Total Noise Including Source Resistors Section 17 | Changes to Figure 11 9 | | Updated Outline Dimensions 24 | Changes to Figure 13, Figure 14, and Figure 16 Captions 10 | | | Changes to Figure 15, Figure 17, and Figure 18 10 | | 2/2013—Rev. L to Rev. M | Changes to Figure 34 and Figure 35 Captions 13 | | Updated Outline Dimensions 21 | Changes to Figure 36 13 | | Changes to Ordering Guide 24 | Changes to Figure 37 Caption 14 | | | Changes to Figure 38 and Figure 41 14 | | 2/2012—Rev. K to Rev. L | Changes to Figure 45 15 | | Changed Functional Block Diagrams Section to Pin | Changes to Audio and PDA Applications Section 18 | | Configuration Section 1 | Changes to Figure 52 18 | | Changes to Figure 11 9 | Changes to Ordering Guide 22 | | Added Figure 33 13 | | | 10/2007—Rev. F to Rev. G | | 8/2011—Rev. J to Rev. K | Changes to Figure 2 1 | | Changes to Figure 20 2 | Updated Outline Dimensions 20 | | Updated Outline Dimensions 20 | 8/2007—Rev. E to Rev. F | | Changes to Ordering Guide 23 | Added 8-Ball WLCSP Package Universal | | 8/2010—Rev. I to Rev. J | Changes to Features 1 | | Changes to Figure 10 and Figure 11 9 | Changes to Table 1 3 | | Changes to Figure 15 10 | Changes to Table 2 5 | | Changes to Figure 36 13 | Changes to Table 4 7 | | Changes to Figure 42 14 | Updated Outline Dimensions 19 | | Updated Outline Dimensions 20 | Changes to Ordering Guide 21 | | Changes to Ordering Guide 23 |

VS = 5 V, VCM = VS/2, TA = 25°C, unless otherwise noted.

Table 1.

Table 3.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

Table 4.

ESD CAUTION

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Input Offset Voltage Distribution

Figure 8. AD8608 Input Offset Voltage Drift Distribution

Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution

Figure 10. Input Offset Voltage vs. Common-Mode Voltage (200 Units, 5 Wafer Lots, Including Process Skews)

Figure 11. Input Bias Current vs. Temperature

Figure 12. Output Saturation Voltage vs. Load Current

Figure 13. Output Voltage Swing High vs. Temperature

Figure 14. Output Voltage Swing Low vs. Temperature

Figure 15. Open-Loop Gain and Phase vs. Frequency

Figure 16. Closed-Loop Output Voltage Swing (FPBW)

Figure 17. Output Impedance vs. Frequency

Figure 18. Common-Mode Rejection Ratio (CMRR) vs. Frequency

Figure 19. PSRR vs. Frequency

Figure 20. Small Signal Overshoot vs. Load Capacitance

Figure 21. Supply Current/Amplifier vs. Temperature

Figure 22. Supply Current/Amplifier vs. Supply Voltage

Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise

Figure 24. Small Signal Transient Response

Figure 25. Large Signal Transient Response

Figure 26. Positive Overload Recovery

Figure 27. Negative Overload Recovery

Figure 28. Voltage Noise Density vs. Frequency

Figure 29. Voltage Noise Density vs. Frequency

Figure 30. Voltage Noise Density vs. Frequency

Figure 31. Input Offset Voltage Distribution

Figure 32. Input Offset Voltage vs. Common-Mode Voltage (200 Units, 5 Wafer Lots, Including Process Skews)

Figure 33. Input Bias Current vs. Temperature

Figure 34. Output Saturation Voltage vs. Load Current

Figure 35. Output Voltage Swing High vs. Temperature

Figure 36. Output Voltage Swing Low vs. Temperature

Figure 37. Open-Loop Gain and Phase vs. Frequency

Figure 38. Closed-Loop Output Voltage Swing vs. Frequency (FPBW)

Figure 39. Output Impedance vs. Frequency

Figure 40. Small Signal Overshoot vs. Load Capacitance

Figure 41. 0.1 Hz to 10 Hz Input Voltage Noise

Figure 42. Small Signal Transient Response

Figure 43. Large Signal Transient Response

Figure 44. Inverting Input Bias Current vs Common-Mode Voltage

Figure 45. Noninverting Input Bias Current vs Common-Mode Voltage