10M08SAE144C8G

Part: Altera MAX 10 FPGAs

Type: Field-Programmable Gate Array

Key Specs:

• Logic Elements: 2K – 50K LEs
• User I/O Pins: Up to 500
• Process Technology: 55 nm embedded NOR flash
• ADC Resolution: 12 bit
• ADC Sample Rate: 1 Msps
• Analog Input Channels: Up to 18
• Dynamic Power Reduction (Sleep Mode): Up to 95%
• Design Security: 128 bit AES

Features:

• Non-volatile instant-on architecture
• Single chip integration
• Embedded SRAM
• High-performance phase-locked loops (PLLs)
• External memory interface (DDR3 SDRAM/DDR3L SDRAM/DDR2 SDRAM/LPDDR2)
• Nios II embedded processor support
• DSP blocks
• 3.3 V, LVDS, PCI, and 30+ other I/O standards supported
• Embedded ADCs
• Temperature sensor
• Single or dual-core voltage supply offering
• Embedded flash (Dual configuration flash, User flash memory)
• Internal oscillator
• Power Saving Features (Sleep mode, Input buffer power-down)
• 128 bit Advanced Encryption Standard (AES) design security
• RoHS6 packaging
• Dual configuration flash
• Soft DDR3 memory controllers

Applications:

• Industrial systems
• Automotive systems
• Control applications in computing
• Control applications in consumer
• Control applications in communications
• Automotive Infotainment
• Industrial Motor Control
• System Management (Power-up sequencing, temperature measurement, interface bridging, I/O expansion)

Package:

• WLCSP: 3 mm, 0.4 mm pitch (V36)
• WLCSP: 4 mm, 0.4 mm pitch (V81)
• FBGA: 17 mm, 1.0 mm pitch (F256)
• UBGA: 15 mm, 0.8 mm pitch (U324)
• FBGA: 23 mm, 1.0 mm pitch (F

• Up to 50,000 logic elements (LEs)
• Maximum of 500 user I/O pins
• Non-volatile instant-on architecture
• Single chip
• Embedded SRAM
• High-performance phase-locked loops (PLLs)
• External memory interface (DDR3 SDRAM/DDR3L SDRAM/DDR2 SDRAM/LPDDR2)
• Nios II embedded processor support
• DSP blocks
• 3.3 V, LVDS, PCI™, and 30+ other I/O standards supported
• Embedded ADCs 12 bit 1 Msps
• Up to 18 analog input channels
• Temperature sensor
• Single or dual-core voltage supply offering
• Embedded flash
  • Dual configuration flash
  • User flash memory
• Internal oscillator
• Power Saving Features
  • Sleep mode to reduce dynamic power by up to 95%
  • Input buffer power-down
• 128 bit Advanced Encryption Standard (AES) design security
• RoHS6 packaging

MAX 10 FPGAs Product Table

Notes:

• 1. Additional user flash may be available, depending on configuration options.
• 1. The number of PLLs available is dependent on the package option.
• 1. Availability of the ADC or TSD varies by package type. Smaller pin-count packages do not have access to the ADC hard IP.
• 1. SRAM only.
• 1. SRAM, DDR3 SDRAM, DDR2 SDRAM, or LPDDR2.
• 1. "D" = Dual power supply (1.2 V/2.5 V), "S" = Single power supply (3.3 V or 3.0 V).
• 1. V81 package does not support analog feature set. 10M08 V81 F devices support dual image with RSU.
• 1. "Easy PCB" utilizes 0.8 mm PCB design rules.
• 1. All data is correct at the time of printing, and may be subject to change without prior notice. For the latest information, please visit www.altera.com.

C, 27, 3/7

Indicates feature set options, GPIO count, and LVDS transmitter or receiver count. Feature set options:

C = Compact (single image), F = Flash (dual image with RSU), A = Analog (analog features block). Each has added premiums.

Indicates pin migration.

• System management Power-up sequencing, temperature measurement
• Interface bridging Translate bus protocol and voltages between incompatible devices
• I/O expansion Increase the available I/O pins of standard devices