10M08SAE144C8G

Part: MAX 10 FPGAs — Altera

Type: Field-Programmable Gate Array (FPGA)

Description: Low-cost, single-chip, non-volatile FPGAs with densities from 2K to 50K LEs, integrated 12-bit 1 Msps ADCs, dual configuration flash, Nios II processor support, and DSP blocks, built on 55 nm embedded NOR flash technology.

Operating Conditions:

• Supply voltage: 1.2 V/2.5 V (dual) or 3.0 V/3.3 V (single)
• Operating temperature: Commercial, Industrial, and Automotive (AEC-Q100) grades
• Logic Elements: 2K to 50K LEs
• User I/O pins: Up to 500

Key Specs:

• Process Technology: 55 nm embedded NOR flash
• Logic Elements (LEs): 2K to 50K
• Block Memory: Up to 1,638 Kb
• User Flash Memory: Up to 736 KB
• 18 x 18 Multipliers: Up to 144
• PLLs: Up to 4
• ADC Resolution: 12 bit
• ADC Sample Rate: 1 Msps

Features:

• Non-volatile instant-on architecture
• Embedded SRAM
• High-performance phase-locked loops (PLLs)
• External memory interface (DDR3 SDRAM/DDR3L SDRAM/DDR2 SDRAM/LPDDR2)
• Nios II embedded processor support
• DSP blocks
• 3.3 V, LVDS, PCI, and 30+ other I/O standards supported
• Embedded ADCs and temperature sensor
• Dual configuration flash and user flash memory
• Internal oscillator
• Power Saving Features (Sleep mode, Input buffer power-down)
• 128 bit Advanced Encryption Standard (AES) design security
• RoHS6 packaging

Applications:

• Automotive Infotainment
• Industrial Motor Control
• System Management Applications

Package:

• WLCSP (3 mm, 0.4 mm pitch)
• WLCSP (4 mm, 0.4 mm pitch)
• FBGA (17 mm, 1.0 mm pitch)
• UBGA (15 mm, 0.8 mm pitch)
• FBGA (23 mm, 1.0 mm pitch)
• FBGA (27 mm, 1.0 mm pitch)
• EQFP (22 mm, 0.5 mm pitch)
• MBGA (8 mm, 0.5 mm pitch)
• UBGA (11 mm, 0.8 mm pitch)

• Up to 50,000 logic elements (LEs)
• Maximum of 500 user I/O pins
• Non-volatile instant-on architecture
• Single chip
• Embedded SRAM
• High-performance phase-locked loops (PLLs)
• External memory interface (DDR3 SDRAM/DDR3L SDRAM/DDR2 SDRAM/LPDDR2)
• Nios II embedded processor support
• DSP blocks
• 3.3 V, LVDS, PCI™, and 30+ other I/O standards supported
• Embedded ADCs - 12 bit 1 Msps
• Up to 18 analog input channels
• Temperature sensor
• Single or dual-core voltage supply offering
• Embedded flash
• Dual configuration flash
• User flash memory
• Internal oscillator
• Power Saving Features
• Sleep mode to reduce dynamic power by up to 95%
• Input buffer power-down
• 128 bit Advanced Encryption Standard (AES) design security
• RoHS6 packaging

• System management - Power-up sequencing, temperature measurement
• Interface bridging - Translate bus protocol and voltages between incompatible devices
• I/O expansion - Increase the available I/O pins of standard devices